Abstract
In this paper we present several algorithms used to construct a tool that automatically optimizes static dataflow graphs for the purpose of high level hardware synthesis. Our target is to automatically merge multiple dataflow graphs in order to create a single structure implementing all distinct operations with minimal area overhead by time-slicing hardware resources. We show that a combination of dedicated optimizations and a simple greedy approach for graph merging reduces the overall area by up to 4x compared to a naive hardware implementation.
Original language | English |
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Title of host publication | Proceedings - 2016 16th International Conference on Embedded Computer Systems |
Subtitle of host publication | Architectures, Modeling and Simulation, SAMOS 2016 |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
Pages | 219-226 |
Number of pages | 8 |
ISBN (Electronic) | 9781509030767 |
DOIs | |
Publication status | Published - 13 Jan 2017 |
Externally published | Yes |
Event | 16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2016 - Samos, Greece Duration: 17 Jul 2016 → 21 Jul 2016 |
Conference
Conference | 16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2016 |
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Country/Territory | Greece |
City | Samos |
Period | 17/07/16 → 21/07/16 |