Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers

C Papameletis; B Keller; V Chickermane; EJ Marinissen; S Hamdioui

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers

C Papameletis, B Keller, V Chickermane, EJ Marinissen, S Hamdioui

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

12 Citations (Scopus)

Original language	English
Title of host publication	18th IEEE European Test Symposium
Editors	s.n.
Place of Publication	Piscataway
Publisher	IEEE Society
Pages	1-6
Number of pages	6
ISBN (Print)	978-1-4673-6377-8
Publication status	Published - 2013
Event	ETS 2013 - Piscataway Duration: 27 May 2013 → 31 May 2013

Publication series

Name
Publisher	IEEE

Conference

Conference	ETS 2013
Period	27/05/13 → 31/05/13

Cite this

@inproceedings{a56a7cc31989483d955adb1729889c04,

title = "Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers",

author = "C Papameletis and B Keller and V Chickermane and EJ Marinissen and S Hamdioui",

year = "2013",

language = "English",

isbn = "978-1-4673-6377-8",

publisher = "IEEE Society",

pages = "1--6",

editor = "s.n.",

booktitle = "18th IEEE European Test Symposium",

note = "ETS 2013 ; Conference date: 27-05-2013 Through 31-05-2013",

}

TY - GEN

T1 - Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers

AU - Papameletis, C

AU - Keller, B

AU - Chickermane, V

AU - Marinissen, EJ

AU - Hamdioui, S

PY - 2013

Y1 - 2013

UR - http://ce-publications.et.tudelft.nl/publications/1417_automated_dft_insertion_and_test_generation_for_3dsics_wit.pdf

M3 - Conference contribution

SN - 978-1-4673-6377-8

SP - 1

EP - 6

BT - 18th IEEE European Test Symposium

A2 - s.n., null

PB - IEEE Society

CY - Piscataway

T2 - ETS 2013

Y2 - 27 May 2013 through 31 May 2013

ER -

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers

Publication series

Conference

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Cite this