Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector

Valery Kritchallo, Billy Braithwaite, Erik Vermij, Koen Bertels, Zaid Al-Ars

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

1 Citation (Scopus)


We present a novel approach to tradeo accuracy against the degree of parallelization for the Canny edge detector, a well-known image-processing algorithm. At the heart of our method is a single top-level image-slicing loop incorporated into the sequential algorithm to process image segments concurrently, a parallelization technique allowing for breaks in the computational continuity in order to achieve high performance levels. By using the delity slider, a new approximate computing concept that we introduce, the user can exercise full control over the desired balance between accuracy of the output and parallel performance. The practical value and strong scalability of the presented method is demonstrated by extensive benchmarks performed on three
evaluation platforms, showing speedups of up to 7x for an accuracy of 100% and up to 19x for an accuracy of 99% over the sequential version, as recorded on an Intel Xeon platform with 14 cores and 28 hardware threads.
Original languageEnglish
Title of host publicationArchitecture of Computing Systems- ARCS 2016
Subtitle of host publicationProceedings of the 29th International Conference on Architecture of Computing Systems
EditorsF. Hannig, J.M.P. Cardoso, T. Pionteck, D. Fey, W. Schröder-Preikschat, J. Teich
Place of PublicationCham
Number of pages12
ISBN (Electronic)978-3-319-30695-7
ISBN (Print)978-3-319-30694-0
Publication statusPublished - 2016
EventArchitecture of Computing Systems, ARCS 2016: 29th International Conference - Nuremberg, Germany
Duration: 4 Apr 20167 Apr 2016

Publication series

NameLecture Notes in Computer Science
PublisherSpringer International Publishing AG
ISSN (Electronic)0302-9743


ConferenceArchitecture of Computing Systems, ARCS 2016


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