@inproceedings{eff59393d9f8416db2deab5fe4fd2795,
title = "Buffer design trade-offs for single electron logic gates",
keywords = "conference contrib. refereed, Conf.proc. > 3 pag",
author = "CR Lageweg and SD Cotofana and S Vassiliadis",
note = "editors onbekend, sb; 5th IEEE Conference on Nanotechnology, Nagoya, Japan ; Conference date: 11-07-2005 Through 15-07-2005",
year = "2005",
language = "Undefined/Unknown",
isbn = "0-7803-9199-3",
publisher = "IEEE Society",
pages = "433--436",
editor = "s.n.",
booktitle = "Proceedings of 2005 5th IEEE Conference on Nanotechnology",
}