Buffer design trade-offs for single electron logic gates

CR Lageweg; SD Cotofana; S Vassiliadis

Buffer design trade-offs for single electron logic gates

CR Lageweg, SD Cotofana, S Vassiliadis

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

5 Citations (Scopus)

Original language	Undefined/Unknown
Title of host publication	Proceedings of 2005 5th IEEE Conference on Nanotechnology
Editors	s.n.
Place of Publication	Piscataway
Publisher	IEEE Society
Pages	433-436
Number of pages	4
ISBN (Print)	0-7803-9199-3
Publication status	Published - 2005
Event	5th IEEE Conference on Nanotechnology, Nagoya, Japan - Piscataway Duration: 11 Jul 2005 → 15 Jul 2005

Publication series

Name
Publisher	IEEE

Conference

Conference	5th IEEE Conference on Nanotechnology, Nagoya, Japan
Period	11/07/05 → 15/07/05

Bibliographical note

editors onbekend, sb

Keywords

conference contrib. refereed
Conf.proc. > 3 pag

Cite this

@inproceedings{eff59393d9f8416db2deab5fe4fd2795,

title = "Buffer design trade-offs for single electron logic gates",

keywords = "conference contrib. refereed, Conf.proc. > 3 pag",

author = "CR Lageweg and SD Cotofana and S Vassiliadis",

note = "editors onbekend, sb; 5th IEEE Conference on Nanotechnology, Nagoya, Japan ; Conference date: 11-07-2005 Through 15-07-2005",

year = "2005",

language = "Undefined/Unknown",

isbn = "0-7803-9199-3",

publisher = "IEEE Society",

pages = "433--436",

editor = "s.n.",

booktitle = "Proceedings of 2005 5th IEEE Conference on Nanotechnology",

}

TY - GEN

T1 - Buffer design trade-offs for single electron logic gates

AU - Lageweg, CR

AU - Cotofana, SD

AU - Vassiliadis, S

N1 - editors onbekend, sb

PY - 2005

Y1 - 2005

KW - conference contrib. refereed

KW - Conf.proc. > 3 pag

M3 - Conference contribution

SN - 0-7803-9199-3

SP - 433

EP - 436

BT - Proceedings of 2005 5th IEEE Conference on Nanotechnology

A2 - s.n., null

PB - IEEE Society

CY - Piscataway

T2 - 5th IEEE Conference on Nanotechnology, Nagoya, Japan

Y2 - 11 July 2005 through 15 July 2005

ER -