Canceling Fundamental Fractional Spurs Due to Self-Interference in a Digital Phase-Locked Loop

Parasitic coupling between the building blocks within a fractional- N phase-locked loop (PLL) can result in noticeable spurs in its output spectrum, thus affecting the PLL’s usability in ultralow jitter applications. In this article, we focus on a chief contributor—“self-interference” caused by coupling from the PLL’s frequency-reference (FREF) clock buffer to the RF oscillator, while exploiting the fact that the resulting phase-disturbance pattern: 1) exhibits a sinusoidal shape and 2) is synchronized with the PLL’s output clock phase. Accordingly, we propose a digitally intensive pattern-aware approach to suppress the fundamental fractional spur raised by this self-interference mechanism. The proposed technique is applied to a fabricated digital PLL chip and reduces the worst spur level by 13 dB, thus proving its effectiveness.