Carbon nanotubes as vertical interconnects for 3D integrated circuits

Sten Vollebregt, Ryoichi Ishihara*

*Corresponding author for this work

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

2 Citations (Scopus)


Currently interconnect technology is the largest contributor to delays in integrated circuits (ICs). By stacking multiple layers of transistors, a process called 3D integration, the length of the interconnects can be reduced considerably. For this, high-aspect ratio, reliable, and low resistance vertical interconnects (vias) are required. Due to their excellent electrical, thermal, and mechanical properties, carbon nanotubes (CNT) are an attractive candidate for this. In this chapter we discuss the application of CNT as vias in 3D IC technology. We start by summarizing the requirements necessary for the successful integration of CNT in semiconductor technology. After this, results from the literature on the application of CNT as vias in traditional IC technology will be reviewed, as most research has so far been focussed on this application. This will be followed by the specific applications of CNT for through-silicon vias and for monolithic 3D IC. Finally the prospects of the application will be discussed.

Original languageEnglish
Title of host publicationCarbon Nanotubes for Interconnects
Subtitle of host publicationProcess, Design and Applications
EditorsA. Todri-Sanial, J. Dijon, A. Maffucci
Place of PublicationCham
Number of pages19
EditionPart II
ISBN (Electronic)978-3-319-29746-0
ISBN (Print)978-3-319-29744-6
Publication statusPublished - 10 Jul 2016


Dive into the research topics of 'Carbon nanotubes as vertical interconnects for 3D integrated circuits'. Together they form a unique fingerprint.

Cite this