Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM

L. Wu, Siddharth Rao, M. Taouil, Erik Jan Marinissen, Gouri Sankar Kar, S. Hamdioui

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

4 Citations (Scopus)
95 Downloads (Pure)


Understanding the defects in magnetic tunnel junctions (MTJs) and their faulty behaviors are paramount for developing high-quality tests for STT-MRAM. This paper characterizes and models intermediate (IM) state defects in MTJs; IM state manifests itself as an abnormal third resistive state, apart from the two bi-stable states of MTJ. We performed silicon measurements on MTJ devices with diameter ranging from 60 nm to 120 nm; the results reveal that the occurrence probability of IM state strongly depends on the switching direction, device size, and applied bias voltage. To test such defect, appropriate fault models are needed. Therefore, we use the advanced device-aware modeling approach, where we first physically model the defect and incorporate it into a Verilog-A MTJ compact model and calibrate it with silicon data. Thereafter, we use a systematic fault analysis to accurately validate a theoretically predefined fault space and derive realistic fault models. Our simulation results show that the IM state defect causes intermittent write transition faults. This paper also demonstrates that the conventional resistor-based fault modeling and test approach fails in appropriately modeling IM defects, and hence incapable of detecting such defects.
Original languageEnglish
Title of host publicationProceedings of the 2021 Design, Automation and Test in Europe, DATE 2021
Number of pages6
ISBN (Electronic)978-3-9819263-5-4
Publication statusPublished - 2021
Event2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) - Virtual, Virtual/Grenoble, France
Duration: 1 Feb 20215 Feb 2021

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591


Conference2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Abbreviated titleDATE'21
Internet address


  • STT-MRAM, intermediate state, manufacturing defects, fault models, device-aware test


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