Abstract
The design of cryogenic interface electronics enabling future scalable quantum computers requires the accurate characterization and modeling of nanometer CMOS processes at cryogenic temperatures. To this end, this paper presents the mismatch characterization of 40-nm bulk CMOS transistors over the temperature range from 300 K down to 4.2 K. Measured data confirm that variability increases at cryogenic temperatures, and analysis of such data proves the validity of both the Pelgrom and the Croon models, which describe the mismatch dependency on device area and bias conditions, respectively.
Original language | English |
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Title of host publication | 48th European Solid-State Device Research Conference, ESSDERC 2018 |
Editors | Frank Ellinger, Thomas Mikolajick, Pawel Grybos |
Publisher | Editions Frontieres |
Pages | 246-249 |
Volume | 2018-September |
ISBN (Electronic) | 9781538654019 |
DOIs | |
Publication status | Published - 2018 |
Event | 48th European Solid-State Device Research Conference, ESSDERC 2018 - Dresden, Germany Duration: 3 Sept 2018 → 6 Sept 2018 |
Conference
Conference | 48th European Solid-State Device Research Conference, ESSDERC 2018 |
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Country/Territory | Germany |
City | Dresden |
Period | 3/09/18 → 6/09/18 |