Characterization and model validation of mismatch in nanometer CMOS at cryogenic temperatures

P. A. T'Hart; J.P.G. van Dijk; M. Babaie; E. Charbon; A. Vladimircscu; F. Sebastiano

doi:10.1109/ESSDERC.2018.8486859

Characterization and model validation of mismatch in nanometer CMOS at cryogenic temperatures

P. A. T'Hart, J.P.G. van Dijk, M. Babaie, E. Charbon, A. Vladimircscu, F. Sebastiano

Electronics

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

34 Citations (Scopus)

Abstract

The design of cryogenic interface electronics enabling future scalable quantum computers requires the accurate characterization and modeling of nanometer CMOS processes at cryogenic temperatures. To this end, this paper presents the mismatch characterization of 40-nm bulk CMOS transistors over the temperature range from 300 K down to 4.2 K. Measured data confirm that variability increases at cryogenic temperatures, and analysis of such data proves the validity of both the Pelgrom and the Croon models, which describe the mismatch dependency on device area and bias conditions, respectively.

Original language	English
Title of host publication	48th European Solid-State Device Research Conference, ESSDERC 2018
Editors	Frank Ellinger, Thomas Mikolajick, Pawel Grybos
Publisher	Editions Frontieres
Pages	246-249
Volume	2018-September
ISBN (Electronic)	9781538654019
DOIs	https://doi.org/10.1109/ESSDERC.2018.8486859
Publication status	Published - 2018
Event	48th European Solid-State Device Research Conference, ESSDERC 2018 - Dresden, Germany Duration: 3 Sept 2018 → 6 Sept 2018

Conference

Conference	48th European Solid-State Device Research Conference, ESSDERC 2018
Country/Territory	Germany
City	Dresden
Period	3/09/18 → 6/09/18

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10.1109/ESSDERC.2018.8486859

Cite this

T'Hart, P. A., van Dijk, J. P. G., Babaie, M., Charbon, E., Vladimircscu, A., & Sebastiano, F. (2018). Characterization and model validation of mismatch in nanometer CMOS at cryogenic temperatures. In F. Ellinger, T. Mikolajick, & P. Grybos (Eds.), 48th European Solid-State Device Research Conference, ESSDERC 2018 (Vol. 2018-September, pp. 246-249). Article 8486859 Editions Frontieres. https://doi.org/10.1109/ESSDERC.2018.8486859

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title = "Characterization and model validation of mismatch in nanometer CMOS at cryogenic temperatures",

abstract = "The design of cryogenic interface electronics enabling future scalable quantum computers requires the accurate characterization and modeling of nanometer CMOS processes at cryogenic temperatures. To this end, this paper presents the mismatch characterization of 40-nm bulk CMOS transistors over the temperature range from 300 K down to 4.2 K. Measured data confirm that variability increases at cryogenic temperatures, and analysis of such data proves the validity of both the Pelgrom and the Croon models, which describe the mismatch dependency on device area and bias conditions, respectively.",

author = "T'Hart, {P. A.} and {van Dijk}, J.P.G. and M. Babaie and E. Charbon and A. Vladimircscu and F. Sebastiano",

year = "2018",

doi = "10.1109/ESSDERC.2018.8486859",

language = "English",

volume = "2018-September",

pages = "246--249",

editor = "Frank Ellinger and Thomas Mikolajick and {Grybos }, {Pawel }",

booktitle = "48th European Solid-State Device Research Conference, ESSDERC 2018",

publisher = "Editions Frontieres",

note = "48th European Solid-State Device Research Conference, ESSDERC 2018 ; Conference date: 03-09-2018 Through 06-09-2018",

}

T'Hart, PA, van Dijk, JPG, Babaie, M , Charbon, E , Vladimircscu, A & Sebastiano, F 2018, Characterization and model validation of mismatch in nanometer CMOS at cryogenic temperatures. in F Ellinger, T Mikolajick & P Grybos (eds), 48th European Solid-State Device Research Conference, ESSDERC 2018. vol. 2018-September, 8486859, Editions Frontieres, pp. 246-249, 48th European Solid-State Device Research Conference, ESSDERC 2018, Dresden, Germany, 3/09/18. https://doi.org/10.1109/ESSDERC.2018.8486859

Characterization and model validation of mismatch in nanometer CMOS at cryogenic temperatures. / T'Hart, P. A.; van Dijk, J.P.G.; Babaie, M. et al.
48th European Solid-State Device Research Conference, ESSDERC 2018. ed. / Frank Ellinger; Thomas Mikolajick; Pawel Grybos . Vol. 2018-September Editions Frontieres, 2018. p. 246-249 8486859.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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N2 - The design of cryogenic interface electronics enabling future scalable quantum computers requires the accurate characterization and modeling of nanometer CMOS processes at cryogenic temperatures. To this end, this paper presents the mismatch characterization of 40-nm bulk CMOS transistors over the temperature range from 300 K down to 4.2 K. Measured data confirm that variability increases at cryogenic temperatures, and analysis of such data proves the validity of both the Pelgrom and the Croon models, which describe the mismatch dependency on device area and bias conditions, respectively.

AB - The design of cryogenic interface electronics enabling future scalable quantum computers requires the accurate characterization and modeling of nanometer CMOS processes at cryogenic temperatures. To this end, this paper presents the mismatch characterization of 40-nm bulk CMOS transistors over the temperature range from 300 K down to 4.2 K. Measured data confirm that variability increases at cryogenic temperatures, and analysis of such data proves the validity of both the Pelgrom and the Croon models, which describe the mismatch dependency on device area and bias conditions, respectively.

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T'Hart PA, van Dijk JPG, Babaie M , Charbon E , Vladimircscu A , Sebastiano F. Characterization and model validation of mismatch in nanometer CMOS at cryogenic temperatures. In Ellinger F, Mikolajick T, Grybos P, editors, 48th European Solid-State Device Research Conference, ESSDERC 2018. Vol. 2018-September. Editions Frontieres. 2018. p. 246-249. 8486859 doi: 10.1109/ESSDERC.2018.8486859

Characterization and model validation of mismatch in nanometer CMOS at cryogenic temperatures

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