Characterization and modeling of mismatch in Cryo-CMOS

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This paper presents a device matching study of a commercial 40-nm bulk CMOS technology operated at cryogenic temperatures. Transistor pairs and linear arrays, optimized for device matching, were characterized over the temperature range from 300 K down to 4.2 K. The device parameters relevant for mismatch, i.e., the threshold voltage and the current factor, were extracted, from which the change in both absolute value and variability as a function of temperature and device size were investigated. It is shown that the Pelgrom scaling law is valid also at 4.2 K and that the simplified Croon model is able to accurately predict drain-current mismatch from moderate to strong inversion over the entire temperature range. Additionally, the characterization of linear device arrays shows exacerbated edge-effects at extremely low temperatures, thus requiring the addition of dummy devices at the array boundary. The result of this study is the first model capable of predicting mismatch over a wide range of operating regions and temperatures.

Original languageEnglish
Article number9015956
Pages (from-to)263-273
Number of pages11
JournalIEEE Journal of the Electron Devices Society
Issue number1
Publication statusPublished - 2020


  • Cryo-CMOS
  • Cryogenics
  • cryogenics
  • Logic gates
  • Mismatch
  • modeling
  • quantum computing.
  • Qubit
  • stress
  • Temperature distribution
  • Temperature sensors


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