Characterization and Test of Intermittent Over RESET in RRAMs

Hanzhi Xun, Moritz Fieback, Sicong Yuan, Hassen Aziza, Mathijs Heidekamp, Thiago Copetti, Leticia Bolzani Poehls, Mottaqiallah Taouil, Said Hamdioui

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Abstract

Resistive Random Access Memories (RRAMs) are being commercialized with significant investment from several semiconductor companies. In order to provide efficient and high-quality test solutions to push high-volume production, a comprehensive understanding of manufacturing defects is significantly required. This paper identifies and characterizes the over-RESET phenomenon based on silicon measurements. In our case study, 30% cycles suffered from intermittent extremely high resistance state exceeding the high resistance state criteria. The paper shows the limitations of conventional defect modeling based on linear resistors. To address this challenge, the Device-Aware (DA) defect modeling method is applied; a model of the defective RRAM device is developed and calibrated using measurements to accurately describe the impact of the defect on the electrical behavior of the memory device. Afterward, fault analysis is performed based on the DA defect model, and appropriate fault models are introduced; they show that the DA defect model will sensitize deep (extremely high resistance) state faults. Finally, dedicated test solutions for over-RESET devices are proposed.
Original languageEnglish
Title of host publicationProceeding of the 2023 IEEE 32nd Asian Test Symposium (ATS)
Place of PublicationPiscataway
PublisherIEEE
Number of pages6
ISBN (Electronic)979-8-3503-0310-0
ISBN (Print)979-8-3503-0311-7
DOIs
Publication statusPublished - 2023
Event2023 IEEE 32nd Asian Test Symposium (ATS) - Beijing, China
Duration: 14 Oct 202317 Oct 2023
Conference number: 32nd

Publication series

NameAsian Test Symposium Proceedings
ISSN (Print)1081-7735
ISSN (Electronic)2377-5386

Conference

Conference2023 IEEE 32nd Asian Test Symposium (ATS)
Country/TerritoryChina
City Beijing
Period14/10/2317/10/23

Bibliographical note

Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Keywords

  • RRAM test
  • device-aware defect model
  • fault modeling
  • Design-for-Testability (DfT)

Fingerprint

Dive into the research topics of 'Characterization and Test of Intermittent Over RESET in RRAMs'. Together they form a unique fingerprint.

Cite this