Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs

Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui

Research output: Contribution to journalArticleScientificpeer-review

Abstract

Understanding defects in magnetic tunnel junctions (MTJs) and their faulty behaviors are paramount for developing high-quality test solutions for STT-MRAM. This article applies the advanced device-aware test to intermediate (IM) state defects in MTJ devices based on silicon measurements and circuit simulations. An IM state manifests itself as an abnormal third resistive state, which differs from the two bi-stable states of MTJ. We performed silicon measurements on MTJ devices with diameter ranging from 60 nm to 120 nm; the results show that the occurrence probability of IM state strongly depends on the switching direction, device size, and bias voltage. We demonstrate that the conventional resistor-based fault modeling and test approach fails to appropriately model and test such a defect. Therefore, device-aware test is applied. We first physically model the defect and incorporate it into a Verilog-A MTJ compact model and calibrate it with silicon data. Thereafter, this model is used for a systematic fault analysis based on circuit simulations to obtain accurate and realistic faults in a pre-defined fault space. Our simulation results show that an IM state defect leads to intermittent write transition faults. Finally, we propose and implement a device-aware test solution to detect the IM state defect.

Original languageEnglish
JournalIEEE Transactions on Computers
DOIs
Publication statusE-pub ahead of print - 2022

Keywords

  • Circuit faults
  • Computational modeling
  • defect characterization
  • device-aware test
  • fault model
  • intermediate state
  • Magnetic tunneling
  • memory test
  • MTJ-internal defect
  • Performance evaluation
  • Resistors
  • Silicon
  • STT-MRAM
  • Switches

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