Chopping in Continuous-Time Sigma-Delta Modulators

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Abstract

This paper discusses the use of chopping in continuous-time sigma-delta modulators where 1/f noise and offset need to be suppressed by continuous-time methods. An intuitive analysis of the artifacts related to chopping is presented. Aliasing of quantization noise is found to be the main problem, especially for chopping frequencies lower than the modulator's sampling frequency (fs). Correctly timed return-to-zero and switched-capacitor DACs are proposed as a solution to the aliasing problem. In both cases, the key idea is to synchronize DAC transitions with moments when the quantization noise at the input of the first integrator is low. Circuit level simulations are presented to validate the proposed techniques.
Original languageEnglish
Title of host publicationConference Proceedings - IEEE International Symposium on Circuits and Systems, ISCAS 2017
Place of PublicationPiscataway, NJ
PublisherIEEE
Pages1-4
Number of pages4
ISBN (Electronic)978-1-4673-6853-7
ISBN (Print)978-1-4673-6852-0
DOIs
Publication statusPublished - 2017
EventISCAS 2017 - IEEE International Symposium on Circuits and Systems: From Dreams to Innovation - Baltimore, MD, United States
Duration: 28 May 201731 May 2017
Conference number: 50
http://iscas2017.org/

Conference

ConferenceISCAS 2017 - IEEE International Symposium on Circuits and Systems
Abbreviated titleISCAS
CountryUnited States
CityBaltimore, MD
Period28/05/1731/05/17
Internet address

Keywords

  • chopping
  • chopping artifacts
  • continuous time
  • sigma delta
  • precision ADC
  • 1/f noise
  • offset

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