Abstract
In modern transceivers, clock generation and planning is one of the key aspects. As a matter of fact, with the increasing occupation of the spectrum and with the increasing use of discrete front ends, non-idealities such as reciprocal mixing are getting more and more critical. This chapter presents the different techniques to enhance the performance of the clock generation especially for all-digital phase locked loops (PLLs) (ADPLLs).
| Original language | English |
|---|---|
| Title of host publication | Digitally Enhanced Mixed Signal Systems |
| Publisher | Institution of Engineering and Technology |
| Pages | 255-288 |
| Number of pages | 34 |
| ISBN (Electronic) | 9781785616099 |
| Publication status | Published - 2019 |