Constraints, hurdles and opportunities for a successful european take-up action

TGRM van Leuken; R Nouta; A van der Graaf

Constraints, hurdles and opportunities for a successful european take-up action

TGRM van Leuken, R Nouta, A van der Graaf

Signal Processing Systems

Research output: Chapter in Book/Conference proceedings/Edited volume › Chapter › Scientific › peer-review

Original language	Undefined/Unknown
Title of host publication	Integrated circuit design: power and timing modeling, optimization and simulation: 10th international workshop, PATMOS 2000 [Lecture notes in computer science 1918]
Editors	D Soudris, P Pirsch, E Barke
Place of Publication	Berlin
Publisher	Springer
Pages	1-2
ISBN (Print)	3-540-41069-6
Publication status	Published - 2000

Keywords

ZX Int.klas.verslagjaar < 2002

Cite this

van Leuken, TGRM ; Nouta, R ; van der Graaf, A. / Constraints, hurdles and opportunities for a successful european take-up action. Integrated circuit design: power and timing modeling, optimization and simulation: 10th international workshop, PATMOS 2000 [Lecture notes in computer science 1918]. editor / D Soudris ; P Pirsch ; E Barke. Berlin : Springer, 2000. pp. 1-2

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year = "2000",

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pages = "1--2",

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booktitle = "Integrated circuit design: power and timing modeling, optimization and simulation: 10th international workshop, PATMOS 2000 [Lecture notes in computer science 1918]",

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Constraints, hurdles and opportunities for a successful european take-up action. / van Leuken, TGRM; Nouta, R; van der Graaf, A.
Integrated circuit design: power and timing modeling, optimization and simulation: 10th international workshop, PATMOS 2000 [Lecture notes in computer science 1918]. ed. / D Soudris; P Pirsch; E Barke. Berlin: Springer, 2000. p. 1-2.

Research output: Chapter in Book/Conference proceedings/Edited volume › Chapter › Scientific › peer-review

TY - CHAP

T1 - Constraints, hurdles and opportunities for a successful european take-up action

AU - van Leuken, TGRM

AU - Nouta, R

AU - van der Graaf, A

PY - 2000

Y1 - 2000

KW - ZX Int.klas.verslagjaar < 2002

M3 - Chapter

SN - 3-540-41069-6

SP - 1

EP - 2

BT - Integrated circuit design: power and timing modeling, optimization and simulation: 10th international workshop, PATMOS 2000 [Lecture notes in computer science 1918]

A2 - D Soudris, null

A2 - P Pirsch, null

A2 - E Barke, null

PB - Springer

CY - Berlin

ER -