Controlled silicon IC thinning on individual die level for active implant integration using a purely mechanical process

Vasiliki Giagka; Nooshin Saeidi; Andreas Demosthenous; Nick Donaldson

doi:10.1109/ECTC.2014.6897610

Controlled silicon IC thinning on individual die level for active implant integration using a purely mechanical process

Vasiliki Giagka^*, Nooshin Saeidi, Andreas Demosthenous, Nick Donaldson

^*Corresponding author for this work

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

5 Citations (Scopus)

Abstract

We are developing an electrode array for epidural spinal cord stimulation and a thin integrated circuit (IC) is to be embedded in it. This paper focuses on the development and characterization of a manual process for thinning individual IC die and discusses the issues associated with thinning small dice by a manual process. The procedure allows easy and controlled post-separation thinning of small (about 1 mm²) silicon chips by grinding. A systematic approach was followed to characterize the technique and repeatability of the results. With the setup we introduced we were able to control the final thickness of the IC with a standard deviation of 9.2 μm. Although no chemical processing is used, a small grit size film can create smooth surfaces, with roughness comparable to reported values after etching, acting as the so-called 'stress-relief' step. Electrical tests performed on a thinned stimulator output stage IC indicated that no die damage was caused by the procedure. Some issues regarding the integration of thinned ICs on flexible substrates and the reliability of gold ball rivet bonds on the ICs' aluminium pads are also discussed.

Original language	English
Title of host publication	Proceedings - Electronic Components and Technology Conference
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	2213-2219
Number of pages	7
ISBN (Electronic)	9781479924073
DOIs	https://doi.org/10.1109/ECTC.2014.6897610
Publication status	Published - 1 Jan 2014
Externally published	Yes
Event	64th Electronic Components and Technology Conference, ECTC 2014 - Orlando, United States Duration: 27 May 2014 → 30 May 2014

Conference

Conference	64th Electronic Components and Technology Conference, ECTC 2014
Country/Territory	United States
City	Orlando
Period	27/05/14 → 30/05/14

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10.1109/ECTC.2014.6897610

Cite this

Giagka, V., Saeidi, N., Demosthenous, A., & Donaldson, N. (2014). Controlled silicon IC thinning on individual die level for active implant integration using a purely mechanical process. In Proceedings - Electronic Components and Technology Conference (pp. 2213-2219). Article 6897610 Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/ECTC.2014.6897610

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author = "Vasiliki Giagka and Nooshin Saeidi and Andreas Demosthenous and Nick Donaldson",

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Giagka, V, Saeidi, N, Demosthenous, A & Donaldson, N 2014, Controlled silicon IC thinning on individual die level for active implant integration using a purely mechanical process. in Proceedings - Electronic Components and Technology Conference., 6897610, Institute of Electrical and Electronics Engineers (IEEE), pp. 2213-2219, 64th Electronic Components and Technology Conference, ECTC 2014, Orlando, United States, 27/05/14. https://doi.org/10.1109/ECTC.2014.6897610

Controlled silicon IC thinning on individual die level for active implant integration using a purely mechanical process. / Giagka, Vasiliki; Saeidi, Nooshin; Demosthenous, Andreas et al.
Proceedings - Electronic Components and Technology Conference. Institute of Electrical and Electronics Engineers (IEEE), 2014. p. 2213-2219 6897610.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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N2 - We are developing an electrode array for epidural spinal cord stimulation and a thin integrated circuit (IC) is to be embedded in it. This paper focuses on the development and characterization of a manual process for thinning individual IC die and discusses the issues associated with thinning small dice by a manual process. The procedure allows easy and controlled post-separation thinning of small (about 1 mm2) silicon chips by grinding. A systematic approach was followed to characterize the technique and repeatability of the results. With the setup we introduced we were able to control the final thickness of the IC with a standard deviation of 9.2 μm. Although no chemical processing is used, a small grit size film can create smooth surfaces, with roughness comparable to reported values after etching, acting as the so-called 'stress-relief' step. Electrical tests performed on a thinned stimulator output stage IC indicated that no die damage was caused by the procedure. Some issues regarding the integration of thinned ICs on flexible substrates and the reliability of gold ball rivet bonds on the ICs' aluminium pads are also discussed.

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Controlled silicon IC thinning on individual die level for active implant integration using a purely mechanical process

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