Convolutional neural networks on dataflow engines

Nils Voss; Marco Bacis; Oskar Mencer; Georgi Gaydadjiev; Wayne Luk

doi:10.1109/ICCD.2017.77

Convolutional neural networks on dataflow engines

Nils Voss^*, Marco Bacis, Oskar Mencer, Georgi Gaydadjiev, Wayne Luk

^*Corresponding author for this work

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

9 Citations (Scopus)

Abstract

In this paper we discuss a high performance implementation for Convolutional Neural Networks (CNNs) inference on the latest generation of Dataflow Engines (DFEs). We discuss the architectural choices made during the design phase taking into account the DFE chip properties. We then perform design space exploration, considering the memory bandwidth and resources utilisation constraints derived from the used DFE and the chosen architecture. Finally, we discuss the high performance implementation and compare the obtained performance against other implementations, showing that our proposed design reaches 2,450 GOPS when running VGG16 as a test case.

Original language	English
Title of host publication	Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	435-438
Number of pages	4
ISBN (Electronic)	9781538622544
DOIs	https://doi.org/10.1109/ICCD.2017.77
Publication status	Published - 22 Nov 2017
Externally published	Yes
Event	35th IEEE International Conference on Computer Design, ICCD 2017 - Boston, United States Duration: 5 Nov 2017 → 8 Nov 2017

Conference

Conference	35th IEEE International Conference on Computer Design, ICCD 2017
Country/Territory	United States
City	Boston
Period	5/11/17 → 8/11/17

Keywords

CNN
Deep Learning
DFE
DSE
FPGA
Inference

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10.1109/ICCD.2017.77

Cite this

@inproceedings{10f150135c5147209849f0e578e6afb5,

title = "Convolutional neural networks on dataflow engines",

abstract = "In this paper we discuss a high performance implementation for Convolutional Neural Networks (CNNs) inference on the latest generation of Dataflow Engines (DFEs). We discuss the architectural choices made during the design phase taking into account the DFE chip properties. We then perform design space exploration, considering the memory bandwidth and resources utilisation constraints derived from the used DFE and the chosen architecture. Finally, we discuss the high performance implementation and compare the obtained performance against other implementations, showing that our proposed design reaches 2,450 GOPS when running VGG16 as a test case.",

keywords = "CNN, Deep Learning, DFE, DSE, FPGA, Inference",

author = "Nils Voss and Marco Bacis and Oskar Mencer and Georgi Gaydadjiev and Wayne Luk",

year = "2017",

month = nov,

day = "22",

doi = "10.1109/ICCD.2017.77",

language = "English",

pages = "435--438",

booktitle = "Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "35th IEEE International Conference on Computer Design, ICCD 2017 ; Conference date: 05-11-2017 Through 08-11-2017",

}

Voss, N, Bacis, M, Mencer, O, Gaydadjiev, G & Luk, W 2017, Convolutional neural networks on dataflow engines. in Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017., 8119250, Institute of Electrical and Electronics Engineers (IEEE), pp. 435-438, 35th IEEE International Conference on Computer Design, ICCD 2017, Boston, United States, 5/11/17. https://doi.org/10.1109/ICCD.2017.77

Convolutional neural networks on dataflow engines. / Voss, Nils; Bacis, Marco; Mencer, Oskar et al.
Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017. Institute of Electrical and Electronics Engineers (IEEE), 2017. p. 435-438 8119250.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Convolutional neural networks on dataflow engines

AU - Voss, Nils

AU - Bacis, Marco

AU - Mencer, Oskar

AU - Gaydadjiev, Georgi

AU - Luk, Wayne

PY - 2017/11/22

Y1 - 2017/11/22

N2 - In this paper we discuss a high performance implementation for Convolutional Neural Networks (CNNs) inference on the latest generation of Dataflow Engines (DFEs). We discuss the architectural choices made during the design phase taking into account the DFE chip properties. We then perform design space exploration, considering the memory bandwidth and resources utilisation constraints derived from the used DFE and the chosen architecture. Finally, we discuss the high performance implementation and compare the obtained performance against other implementations, showing that our proposed design reaches 2,450 GOPS when running VGG16 as a test case.

AB - In this paper we discuss a high performance implementation for Convolutional Neural Networks (CNNs) inference on the latest generation of Dataflow Engines (DFEs). We discuss the architectural choices made during the design phase taking into account the DFE chip properties. We then perform design space exploration, considering the memory bandwidth and resources utilisation constraints derived from the used DFE and the chosen architecture. Finally, we discuss the high performance implementation and compare the obtained performance against other implementations, showing that our proposed design reaches 2,450 GOPS when running VGG16 as a test case.

KW - CNN

KW - Deep Learning

KW - DFE

KW - DSE

KW - FPGA

KW - Inference

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U2 - 10.1109/ICCD.2017.77

DO - 10.1109/ICCD.2017.77

M3 - Conference contribution

AN - SCOPUS:85041669324

SP - 435

EP - 438

BT - Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017

PB - Institute of Electrical and Electronics Engineers (IEEE)

T2 - 35th IEEE International Conference on Computer Design, ICCD 2017

Y2 - 5 November 2017 through 8 November 2017

ER -

Convolutional neural networks on dataflow engines

Abstract

Conference

Keywords

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