The increased use of mobile appliances such as mobile phones and navigation systems in today's society has resulted in an increase in reliability issues related to drop performance. Mobile appliances are dropped several times during their lifespan and the product is required to survive common drop accidents. A widely accepted method to assess the drop reliability of microelectronics on board-level is the drop impact test. this test had been standardized by international councils such as Joint Electron Device Engineering Council and is widely adopted throughout the industry. In this research the solder loading is investigated by combining high-speed camera measurements of several drop impact tests with verified finite element models. These simulation models are developed in order to gain an insight in the loading pattern of solder joints based on interconnect layout, drop conditions, and product specifications prior to physical prototyping. Deflections and frequencies during drop testing are measured using a high-speed camera setup. The high-speed camera experiments are performed on two levels: machine level (rebounds with and without a catcher) and product level (with different levels of energy and different pulse times). Parametric (dyanamic and quasistatic) 3D models are developed to predict the drop impact performance. The experimental results are used to verify and enhance the simulation models, e.g. by tuning the damping parameters. As a result, the verified models can be used to determine the location of the critical solder joint and to obtain estimates of the solder lifetime performance. Keywords: drop impact reliability, drop impact modeling, chip scale packages, high-speed camera experiment.
|Number of pages||9|
|Journal||Journal of Electronic Packaging|
|Publication status||Published - 2009|
- academic journal papers
- CWTS JFIS < 0.75