Coupling of a reconfigurable architecture and a multithread processor core with integrated real-time

S Uhrig; S Maier; GK Kuzmanov; P Ungerer

Coupling of a reconfigurable architecture and a multithread processor core with integrated real-time

S Uhrig, S Maier, GK Kuzmanov, P Ungerer

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

Original language	Undefined/Unknown
Title of host publication	Proceedings of the 20th IEEE International Parallel & Distributed Processing Symposium
Editors	s.n.
Place of Publication	Piscataway
Publisher	IEEE Society
Pages	209-209
ISBN (Print)	1-4244-0054-6
Publication status	Published - 2006
Event	IPDPS2006 - Piscataway Duration: 25 Apr 2006 → 29 Apr 2006

Publication series

Name
Publisher	IEEE

Conference

Conference	IPDPS2006
Period	25/04/06 → 29/04/06

Keywords

Elektrotechniek
Techniek
conference contrib. refereed
Conf.proc. > 3 pag

Cite this

@inproceedings{b9cfa292a8cf438493db2eef3d3f2522,

title = "Coupling of a reconfigurable architecture and a multithread processor core with integrated real-time",

keywords = "Elektrotechniek, Techniek, conference contrib. refereed, Conf.proc. > 3 pag",

author = "S Uhrig and S Maier and GK Kuzmanov and P Ungerer",

year = "2006",

language = "Undefined/Unknown",

isbn = "1-4244-0054-6",

publisher = "IEEE Society",

pages = "209--209",

editor = "s.n.",

booktitle = "Proceedings of the 20th IEEE International Parallel & Distributed Processing Symposium",

note = "null ; Conference date: 25-04-2006 Through 29-04-2006",

}

Coupling of a reconfigurable architecture and a multithread processor core with integrated real-time. / Uhrig, S; Maier, S; Kuzmanov, GK; Ungerer, P.

Proceedings of the 20th IEEE International Parallel & Distributed Processing Symposium. ed. / s.n. Piscataway : IEEE Society, 2006. p. 209-209.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Coupling of a reconfigurable architecture and a multithread processor core with integrated real-time

AU - Uhrig, S

AU - Maier, S

AU - Kuzmanov, GK

AU - Ungerer, P

PY - 2006

Y1 - 2006

KW - Elektrotechniek

KW - Techniek

KW - conference contrib. refereed

KW - Conf.proc. > 3 pag

M3 - Conference contribution

SN - 1-4244-0054-6

SP - 209

EP - 209

BT - Proceedings of the 20th IEEE International Parallel & Distributed Processing Symposium

A2 - s.n., null

PB - IEEE Society

CY - Piscataway

Y2 - 25 April 2006 through 29 April 2006

ER -