Cryo-CMOS Electronic Control for Scalable Quantum Computing: Invited

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16 Citations (Scopus)

Abstract

Quantum computers1 could revolutionize computing in a profound way due to the massive speedup they promise. A quantum computer comprises a cryogenic quantum processor and a classical electronic controller. When scaling up the cryogenic quantum processor to at least a few thousands, and possibly millions, of qubits required for any practical quantum algorithm, cryogenic CMOS (cryo-CMOS) electronics is required to allow feasible and compact interconnections between the controller and the quantum processor. Cryo-CMOS leverages the CMOS fabrication infrastructure while exploiting the continuous improvement of performance and miniaturization guaranteed by Moore's law, in order to enable the fabrication of a cost-effective practical quantum computer. However, designing cryo-CMOS integrated circuits requires a new set of CMOS device models, their embedding in design and verification tools, and the possibility to co-simulate the cryo-CMOS/quantum-processor architecture for full-system optimization. In this paper, we address these challenges by focusing on their impact on the design of complex cryo-CMOS systems.

Original languageEnglish
Title of host publicationProceedings of the 54th Annual Design Automation Conference 2017, DAC 2017
Place of PublicationNew York, NY
PublisherAssociation for Computing Machinery (ACM)
VolumePart 128280
ISBN (Electronic)978-1-4503-4927-7
DOIs
Publication statusPublished - 2017
Event54th Annual Design Automation Conference, DAC 2017 - Austin, United States
Duration: 18 Jun 201722 Jun 2017

Conference

Conference54th Annual Design Automation Conference, DAC 2017
CountryUnited States
CityAustin
Period18/06/1722/06/17

Keywords

  • Cryo-CMOS
  • cryogenics
  • device models
  • error-correcting loop
  • quantum computation
  • qubit

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