Cryo-CMOS for Quantum Computing

E. Charbon; F. Sebastiano; A. Vladimirescu; H. Homulle; S. Visser; L. Song; R.M. Incandela

doi:10.1109/IEDM.2016.7838410

Cryo-CMOS for Quantum Computing

E. Charbon, F. Sebastiano, A. Vladimirescu, H. Homulle, S. Visser, L. Song, R.M. Incandela

Electronic Instrumentation

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

90 Citations (Scopus)

Abstract

Cryogenic CMOS, or cryo-CMOS circuits and systems, are emerging in VLSI design for many applications, in primis quantum computing. Fault-tolerant quantum bits (qubits) in surface code configurations, one of the most accepted implementations in quantum computing, operate in deep sub-Kelvin regime and require scalable classical control circuits. In this paper we advocate the need for a new generation of deep-submicron CMOS circuits operating at deep-cryogenic temperatures to achieve the performance required in a fault-tolerant qubit system. We outline the challenges and limitations of operating CMOS in near-zero Kelvin regimes and we propose solutions. The paper concludes with several examples showing the suitability of integrating fault-tolerant.qubits with CMOS.

Original language	English
Title of host publication	2016 IEEE International Electron Devices Meeting, IEDM 2016
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	343-346
Number of pages	4
ISBN (Electronic)	978-1-5090-3902-9
DOIs	https://doi.org/10.1109/IEDM.2016.7838410
Publication status	Published - 2017
Event	IEDM 2016: 62nd IEEE International Electron Devices Meeting - San Francisco, CA, United States Duration: 3 Dec 2016 → 7 Dec 2016 Conference number: 62 http://ieee-iedm.org/

Conference

Conference	IEDM 2016
Abbreviated title	IEDM
Country/Territory	United States
City	San Francisco, CA
Period	3/12/16 → 7/12/16
Internet address	http://ieee-iedm.org/

Bibliographical note

13.5

Keywords

Quantum dots
Quantum computing
Multiplexing
Field programmable gate arrays
Fault tolerance
Fault tolerant system
Computers

Access to Document

10.1109/IEDM.2016.7838410

Cite this

@inproceedings{8c0a39a0647d4ebaa7153703ced83865,

title = "Cryo-CMOS for Quantum Computing",

abstract = "Cryogenic CMOS, or cryo-CMOS circuits and systems, are emerging in VLSI design for many applications, in primis quantum computing. Fault-tolerant quantum bits (qubits) in surface code configurations, one of the most accepted implementations in quantum computing, operate in deep sub-Kelvin regime and require scalable classical control circuits. In this paper we advocate the need for a new generation of deep-submicron CMOS circuits operating at deep-cryogenic temperatures to achieve the performance required in a fault-tolerant qubit system. We outline the challenges and limitations of operating CMOS in near-zero Kelvin regimes and we propose solutions. The paper concludes with several examples showing the suitability of integrating fault-tolerant.qubits with CMOS.",

keywords = "Quantum dots, Quantum computing, Multiplexing, Field programmable gate arrays, Fault tolerance, Fault tolerant system, Computers ",

author = "E. Charbon and F. Sebastiano and A. Vladimirescu and H. Homulle and S. Visser and L. Song and R.M. Incandela",

note = "13.5; IEDM 2016 : 62nd IEEE International Electron Devices Meeting , IEDM ; Conference date: 03-12-2016 Through 07-12-2016",

year = "2017",

doi = "10.1109/IEDM.2016.7838410",

language = "English",

pages = "343--346",

booktitle = "2016 IEEE International Electron Devices Meeting, IEDM 2016",

publisher = "IEEE",

address = "United States",

url = "http://ieee-iedm.org/",

}

TY - GEN

T1 - Cryo-CMOS for Quantum Computing

AU - Charbon, E.

AU - Sebastiano, F.

AU - Vladimirescu, A.

AU - Homulle, H.

AU - Visser, S.

AU - Song, L.

AU - Incandela, R.M.

N1 - Conference code: 62

PY - 2017

Y1 - 2017

N2 - Cryogenic CMOS, or cryo-CMOS circuits and systems, are emerging in VLSI design for many applications, in primis quantum computing. Fault-tolerant quantum bits (qubits) in surface code configurations, one of the most accepted implementations in quantum computing, operate in deep sub-Kelvin regime and require scalable classical control circuits. In this paper we advocate the need for a new generation of deep-submicron CMOS circuits operating at deep-cryogenic temperatures to achieve the performance required in a fault-tolerant qubit system. We outline the challenges and limitations of operating CMOS in near-zero Kelvin regimes and we propose solutions. The paper concludes with several examples showing the suitability of integrating fault-tolerant.qubits with CMOS.

AB - Cryogenic CMOS, or cryo-CMOS circuits and systems, are emerging in VLSI design for many applications, in primis quantum computing. Fault-tolerant quantum bits (qubits) in surface code configurations, one of the most accepted implementations in quantum computing, operate in deep sub-Kelvin regime and require scalable classical control circuits. In this paper we advocate the need for a new generation of deep-submicron CMOS circuits operating at deep-cryogenic temperatures to achieve the performance required in a fault-tolerant qubit system. We outline the challenges and limitations of operating CMOS in near-zero Kelvin regimes and we propose solutions. The paper concludes with several examples showing the suitability of integrating fault-tolerant.qubits with CMOS.

KW - Quantum dots

KW - Quantum computing

KW - Multiplexing

KW - Field programmable gate arrays

KW - Fault tolerance

KW - Fault tolerant system

KW - Computers

U2 - 10.1109/IEDM.2016.7838410

DO - 10.1109/IEDM.2016.7838410

M3 - Conference contribution

SP - 343

EP - 346

BT - 2016 IEEE International Electron Devices Meeting, IEDM 2016

PB - IEEE

CY - Piscataway, NJ

T2 - IEDM 2016

Y2 - 3 December 2016 through 7 December 2016

ER -

Cryo-CMOS for Quantum Computing

Abstract

Conference

Bibliographical note

Keywords

Access to Document

Fingerprint

Cite this