Cryogenic Comparator Characterization and Modeling for a Cryo-CMOS 7b 1-GSa/s SAR ADC

Gerd Kiene; Aishwarya Gunaputi Sreenivasulu; Ramon W.J. Overwater; Masoud Babaie; Fabio Sebastiano

doi:10.1109/ESSCIRC55480.2022.9911474

Cryogenic Comparator Characterization and Modeling for a Cryo-CMOS 7b 1-GSa/s SAR ADC

Gerd Kiene, Aishwarya Gunaputi Sreenivasulu, Ramon W.J. Overwater, Masoud Babaie, Fabio Sebastiano

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

3 Citations (Scopus)

26 Downloads (Pure)

Abstract

This paper reports the experimental characterization and modelling of a stand-Alone StrongARM comparator at both room temperature (RT) and cryogenic temperature (4.2 K). The observed 6-dB improvement in the comparator input noise at 4.2 K is attributed to the reduction of the thermal noise and to the suppressed shot noise in the MOS transistors becoming dominant at cryogenic temperature. The proposed model is employed in the design of a loop-unrolled 2\times time-interleaved 1-GSa/s 7b SAR ADC for spin-qubit readout. As predicted by the comparator model, the ADC is noise-limited at RT to a SNDR of 38.2 dB at Nyquist input, while this improves to 41.1 dB at 4.2 K, now limited by distortion, thus resulting in the state-of-The-Art FoMw for cryo-CMOS ADC of 20.9 fJ/conv-step.

Original language	English
Title of host publication	ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	53-56
Number of pages	4
ISBN (Electronic)	978-1-6654-8494-7
DOIs	https://doi.org/10.1109/ESSCIRC55480.2022.9911474
Publication status	Published - 2022
Event	48th IEEE European Solid State Circuits Conference, ESSCIRC 2022 - Milan, Italy Duration: 19 Sept 2022 → 22 Sept 2022

Publication series

Name	ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings

Conference

Conference	48th IEEE European Solid State Circuits Conference, ESSCIRC 2022
Country/Territory	Italy
City	Milan
Period	19/09/22 → 22/09/22

Bibliographical note

Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Keywords

ADC
Cryo-CMOS
latching comparator
noise measurement
SAR
strongARM

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10.1109/ESSCIRC55480.2022.9911474

Cryogenic_Comparator_Characterization_and_Modeling_for_a_Cryo-CMOS_7b_1-GSa_s_SAR_ADCFinal published version, 4.92 MB

Cite this

Kiene, G., Sreenivasulu, A. G., Overwater, R. W. J., Babaie, M., & Sebastiano, F. (2022). Cryogenic Comparator Characterization and Modeling for a Cryo-CMOS 7b 1-GSa/s SAR ADC. In ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings (pp. 53-56). (ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/ESSCIRC55480.2022.9911474

Kiene, Gerd ; Sreenivasulu, Aishwarya Gunaputi ; Overwater, Ramon W.J. et al. / Cryogenic Comparator Characterization and Modeling for a Cryo-CMOS 7b 1-GSa/s SAR ADC. ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings. Institute of Electrical and Electronics Engineers (IEEE), 2022. pp. 53-56 (ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings).

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title = "Cryogenic Comparator Characterization and Modeling for a Cryo-CMOS 7b 1-GSa/s SAR ADC",

abstract = "This paper reports the experimental characterization and modelling of a stand-Alone StrongARM comparator at both room temperature (RT) and cryogenic temperature (4.2 K). The observed 6-dB improvement in the comparator input noise at 4.2 K is attributed to the reduction of the thermal noise and to the suppressed shot noise in the MOS transistors becoming dominant at cryogenic temperature. The proposed model is employed in the design of a loop-unrolled 2\times time-interleaved 1-GSa/s 7b SAR ADC for spin-qubit readout. As predicted by the comparator model, the ADC is noise-limited at RT to a SNDR of 38.2 dB at Nyquist input, while this improves to 41.1 dB at 4.2 K, now limited by distortion, thus resulting in the state-of-The-Art FoMw for cryo-CMOS ADC of 20.9 fJ/conv-step. ",

keywords = "ADC, Cryo-CMOS, latching comparator, noise measurement, SAR, strongARM",

author = "Gerd Kiene and Sreenivasulu, {Aishwarya Gunaputi} and Overwater, {Ramon W.J.} and Masoud Babaie and Fabio Sebastiano",

note = "Green Open Access added to TU Delft Institutional Repository {\textquoteleft}You share, we take care!{\textquoteright} – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.; 48th IEEE European Solid State Circuits Conference, ESSCIRC 2022 ; Conference date: 19-09-2022 Through 22-09-2022",

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Kiene, G, Sreenivasulu, AG, Overwater, RWJ , Babaie, M & Sebastiano, F 2022, Cryogenic Comparator Characterization and Modeling for a Cryo-CMOS 7b 1-GSa/s SAR ADC. in ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings. ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings, Institute of Electrical and Electronics Engineers (IEEE), pp. 53-56, 48th IEEE European Solid State Circuits Conference, ESSCIRC 2022, Milan, Italy, 19/09/22. https://doi.org/10.1109/ESSCIRC55480.2022.9911474

Cryogenic Comparator Characterization and Modeling for a Cryo-CMOS 7b 1-GSa/s SAR ADC. / Kiene, Gerd; Sreenivasulu, Aishwarya Gunaputi; Overwater, Ramon W.J. et al.
ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings. Institute of Electrical and Electronics Engineers (IEEE), 2022. p. 53-56 (ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings).

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Cryogenic Comparator Characterization and Modeling for a Cryo-CMOS 7b 1-GSa/s SAR ADC

AU - Kiene, Gerd

AU - Sreenivasulu, Aishwarya Gunaputi

AU - Overwater, Ramon W.J.

AU - Babaie, Masoud

AU - Sebastiano, Fabio

N1 - Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

PY - 2022

Y1 - 2022

N2 - This paper reports the experimental characterization and modelling of a stand-Alone StrongARM comparator at both room temperature (RT) and cryogenic temperature (4.2 K). The observed 6-dB improvement in the comparator input noise at 4.2 K is attributed to the reduction of the thermal noise and to the suppressed shot noise in the MOS transistors becoming dominant at cryogenic temperature. The proposed model is employed in the design of a loop-unrolled 2\times time-interleaved 1-GSa/s 7b SAR ADC for spin-qubit readout. As predicted by the comparator model, the ADC is noise-limited at RT to a SNDR of 38.2 dB at Nyquist input, while this improves to 41.1 dB at 4.2 K, now limited by distortion, thus resulting in the state-of-The-Art FoMw for cryo-CMOS ADC of 20.9 fJ/conv-step.

AB - This paper reports the experimental characterization and modelling of a stand-Alone StrongARM comparator at both room temperature (RT) and cryogenic temperature (4.2 K). The observed 6-dB improvement in the comparator input noise at 4.2 K is attributed to the reduction of the thermal noise and to the suppressed shot noise in the MOS transistors becoming dominant at cryogenic temperature. The proposed model is employed in the design of a loop-unrolled 2\times time-interleaved 1-GSa/s 7b SAR ADC for spin-qubit readout. As predicted by the comparator model, the ADC is noise-limited at RT to a SNDR of 38.2 dB at Nyquist input, while this improves to 41.1 dB at 4.2 K, now limited by distortion, thus resulting in the state-of-The-Art FoMw for cryo-CMOS ADC of 20.9 fJ/conv-step.

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KW - Cryo-CMOS

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M3 - Conference contribution

AN - SCOPUS:85141529200

T3 - ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings

SP - 53

EP - 56

BT - ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings

PB - Institute of Electrical and Electronics Engineers (IEEE)

T2 - 48th IEEE European Solid State Circuits Conference, ESSCIRC 2022

Y2 - 19 September 2022 through 22 September 2022

ER -

Kiene G, Sreenivasulu AG, Overwater RWJ , Babaie M , Sebastiano F. Cryogenic Comparator Characterization and Modeling for a Cryo-CMOS 7b 1-GSa/s SAR ADC. In ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings. Institute of Electrical and Electronics Engineers (IEEE). 2022. p. 53-56. (ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings). doi: 10.1109/ESSCIRC55480.2022.9911474

Cryogenic Comparator Characterization and Modeling for a Cryo-CMOS 7b 1-GSa/s SAR ADC

Abstract

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Keywords

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