TY - GEN
T1 - Cryogenic Comparator Characterization and Modeling for a Cryo-CMOS 7b 1-GSa/s SAR ADC
AU - Kiene, Gerd
AU - Sreenivasulu, Aishwarya Gunaputi
AU - Overwater, Ramon W.J.
AU - Babaie, Masoud
AU - Sebastiano, Fabio
N1 - Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.
PY - 2022
Y1 - 2022
N2 - This paper reports the experimental characterization and modelling of a stand-Alone StrongARM comparator at both room temperature (RT) and cryogenic temperature (4.2 K). The observed 6-dB improvement in the comparator input noise at 4.2 K is attributed to the reduction of the thermal noise and to the suppressed shot noise in the MOS transistors becoming dominant at cryogenic temperature. The proposed model is employed in the design of a loop-unrolled 2\times time-interleaved 1-GSa/s 7b SAR ADC for spin-qubit readout. As predicted by the comparator model, the ADC is noise-limited at RT to a SNDR of 38.2 dB at Nyquist input, while this improves to 41.1 dB at 4.2 K, now limited by distortion, thus resulting in the state-of-The-Art FoMw for cryo-CMOS ADC of 20.9 fJ/conv-step.
AB - This paper reports the experimental characterization and modelling of a stand-Alone StrongARM comparator at both room temperature (RT) and cryogenic temperature (4.2 K). The observed 6-dB improvement in the comparator input noise at 4.2 K is attributed to the reduction of the thermal noise and to the suppressed shot noise in the MOS transistors becoming dominant at cryogenic temperature. The proposed model is employed in the design of a loop-unrolled 2\times time-interleaved 1-GSa/s 7b SAR ADC for spin-qubit readout. As predicted by the comparator model, the ADC is noise-limited at RT to a SNDR of 38.2 dB at Nyquist input, while this improves to 41.1 dB at 4.2 K, now limited by distortion, thus resulting in the state-of-The-Art FoMw for cryo-CMOS ADC of 20.9 fJ/conv-step.
KW - ADC
KW - Cryo-CMOS
KW - latching comparator
KW - noise measurement
KW - SAR
KW - strongARM
UR - http://www.scopus.com/inward/record.url?scp=85141529200&partnerID=8YFLogxK
U2 - 10.1109/ESSCIRC55480.2022.9911474
DO - 10.1109/ESSCIRC55480.2022.9911474
M3 - Conference contribution
AN - SCOPUS:85141529200
T3 - ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings
SP - 53
EP - 56
BT - ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings
PB - IEEE
T2 - 48th IEEE European Solid State Circuits Conference, ESSCIRC 2022
Y2 - 19 September 2022 through 22 September 2022
ER -