Resistive Random Access Memory (RRAM) is a potential technology to replace conventional memories by providing low power consumption and high-density storage. As various manufacturing vendors make significant efforts to push it to high-volume production and commercialization, high-quality and efficient test solutions are of great importance. This paper analyzes interconnect and contact defects in RRAMs, while considering the impact of the memory Data Background (DB), and proposes test solutions. The complete interconnect and contact defect space in a layout-independent RRAM design is defined. Exhaustive defect injection and circuit simulation are performed in a systematic manner to derive appropriate fault models, not only for single-cell and two-cell coupling faults, but also for multi-cell coupling faults where the DBs are important. The results show the existence of unique 3-cell and 4-cell coupling faults due to e.g., the sneak path in the array induced by defects. These unique faults cannot be detected with traditional RRAM test solutions. Therefore, the paper introduces a test generation method that takes into account the DB, which is able to efficiently detect all these faults; hence, further improving the fault/defect coverage in RRAMs.
|Title of host publication
|Proceedings of the 2023 IEEE European Test Symposium (ETS)
|Number of pages
|Published - 2023
|2023 IEEE European Test Symposium (ETS) - Venezia, Italy
Duration: 22 May 2023 → 26 May 2023
|Proceedings of the European Test Workshop
|2023 IEEE European Test Symposium (ETS)
|22/05/23 → 26/05/23
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- interconnect and contact defects
- data background
- fault models
- test development