Defects, Fault Modeling, and Test Development Framework for FeFETs

Changhao Wang; Sicong Yuan; Hanzhi Xun; Chaobo Li; Mottaqiallah Taouil; Moritz Fieback; Danyang Chen; Xiuyan Li; Lin Wang; Riccardo Cantoro; Chujun Yin; Said Hamdioui

doi:10.1109/ITC51657.2024.00026

Defects, Fault Modeling, and Test Development Framework for FeFETs

Changhao Wang^*, Sicong Yuan, Hanzhi Xun, Chaobo Li, Mottaqiallah Taouil, Moritz Fieback, Danyang Chen, Xiuyan Li, Lin Wang, Riccardo Cantoro, Chujun Yin, Said Hamdioui

^*Corresponding author for this work

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

Abstract

As emerging non-volatile memory (NVM) devices, Ferroelectric Field-Effect Transistors (FeFETs) present distinctive opportunities for the design of ultra-dense and low-leakage memory systems. For matured FeFET manufacturing, it is extremely important to have an understanding of manufacturing defects and accurately model them to develop effective test solutions. This paper introduces a comprehensive framework for defect and fault modeling, which enables the development of test solutions. First, a classification of FeFET manufacturing defects is provided; both conventional defects (such as contacts and interconnect defects) as well as unique FeFET defects are discussed. The latter FeFET specific defect leads to unique faults that cannot be adequately described using traditional modeling approaches. Then, the Device-Aware Test (DAT) method is used to effectively and appropriately model, analyze and develop test solutions for such unique defects; the approach will be illustrated for Stuck-at-Polarization (SAP) defects.

Original language	English
Title of host publication	Proceedings - 2024 IEEE International Test Conference, ITC 2024
Publisher	IEEE
Pages	91-95
Number of pages	5
ISBN (Electronic)	9798331520137
DOIs	https://doi.org/10.1109/ITC51657.2024.00026
Publication status	Published - 2024
Event	2024 IEEE International Test Conference, ITC 2024 - San Diego, United States Duration: 3 Nov 2024 → 8 Nov 2024

Publication series

Name	Proceedings - International Test Conference
ISSN (Print)	1089-3539

Conference

Conference	2024 IEEE International Test Conference, ITC 2024
Country/Territory	United States
City	San Diego
Period	3/11/24 → 8/11/24

Bibliographical note

Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Keywords

defect modeling
device-aware defect model
fault modeling
fefet
memory test

Access to Document

10.1109/ITC51657.2024.00026

Defects_Fault_Modeling_and_Test_Development_Framework_for_FeFETsFinal published version, 2.68 MB

Cite this

Wang, C., Yuan, S., Xun, H., Li, C., Taouil, M., Fieback, M., Chen, D., Li, X., Wang, L., Cantoro, R., Yin, C., & Hamdioui, S. (2024). Defects, Fault Modeling, and Test Development Framework for FeFETs. In Proceedings - 2024 IEEE International Test Conference, ITC 2024 (pp. 91-95). (Proceedings - International Test Conference). IEEE. https://doi.org/10.1109/ITC51657.2024.00026

@inproceedings{af4f4655c8594b478b1a9400c7743af3,

title = "Defects, Fault Modeling, and Test Development Framework for FeFETs",

abstract = "As emerging non-volatile memory (NVM) devices, Ferroelectric Field-Effect Transistors (FeFETs) present distinctive opportunities for the design of ultra-dense and low-leakage memory systems. For matured FeFET manufacturing, it is extremely important to have an understanding of manufacturing defects and accurately model them to develop effective test solutions. This paper introduces a comprehensive framework for defect and fault modeling, which enables the development of test solutions. First, a classification of FeFET manufacturing defects is provided; both conventional defects (such as contacts and interconnect defects) as well as unique FeFET defects are discussed. The latter FeFET specific defect leads to unique faults that cannot be adequately described using traditional modeling approaches. Then, the Device-Aware Test (DAT) method is used to effectively and appropriately model, analyze and develop test solutions for such unique defects; the approach will be illustrated for Stuck-at-Polarization (SAP) defects.",

keywords = "defect modeling, device-aware defect model, fault modeling, fefet, memory test",

author = "Changhao Wang and Sicong Yuan and Hanzhi Xun and Chaobo Li and Mottaqiallah Taouil and Moritz Fieback and Danyang Chen and Xiuyan Li and Lin Wang and Riccardo Cantoro and Chujun Yin and Said Hamdioui",

note = "Green Open Access added to TU Delft Institutional Repository {\textquoteleft}You share, we take care!{\textquoteright} – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public. ; 2024 IEEE International Test Conference, ITC 2024 ; Conference date: 03-11-2024 Through 08-11-2024",

year = "2024",

doi = "10.1109/ITC51657.2024.00026",

language = "English",

series = "Proceedings - International Test Conference",

publisher = "IEEE",

pages = "91--95",

booktitle = "Proceedings - 2024 IEEE International Test Conference, ITC 2024",

address = "United States",

}

Wang, C, Yuan, S , Xun, H, Li, C, Taouil, M , Fieback, M, Chen, D, Li, X, Wang, L, Cantoro, R, Yin, C & Hamdioui, S 2024, Defects, Fault Modeling, and Test Development Framework for FeFETs. in Proceedings - 2024 IEEE International Test Conference, ITC 2024. Proceedings - International Test Conference, IEEE, pp. 91-95, 2024 IEEE International Test Conference, ITC 2024, San Diego, United States, 3/11/24. https://doi.org/10.1109/ITC51657.2024.00026

Defects, Fault Modeling, and Test Development Framework for FeFETs. / Wang, Changhao; Yuan, Sicong ; Xun, Hanzhi et al.
Proceedings - 2024 IEEE International Test Conference, ITC 2024. IEEE, 2024. p. 91-95 (Proceedings - International Test Conference).

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Defects, Fault Modeling, and Test Development Framework for FeFETs

AU - Wang, Changhao

AU - Yuan, Sicong

AU - Xun, Hanzhi

AU - Li, Chaobo

AU - Taouil, Mottaqiallah

AU - Fieback, Moritz

AU - Chen, Danyang

AU - Li, Xiuyan

AU - Wang, Lin

AU - Cantoro, Riccardo

AU - Yin, Chujun

AU - Hamdioui, Said

N1 - Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

PY - 2024

Y1 - 2024

N2 - As emerging non-volatile memory (NVM) devices, Ferroelectric Field-Effect Transistors (FeFETs) present distinctive opportunities for the design of ultra-dense and low-leakage memory systems. For matured FeFET manufacturing, it is extremely important to have an understanding of manufacturing defects and accurately model them to develop effective test solutions. This paper introduces a comprehensive framework for defect and fault modeling, which enables the development of test solutions. First, a classification of FeFET manufacturing defects is provided; both conventional defects (such as contacts and interconnect defects) as well as unique FeFET defects are discussed. The latter FeFET specific defect leads to unique faults that cannot be adequately described using traditional modeling approaches. Then, the Device-Aware Test (DAT) method is used to effectively and appropriately model, analyze and develop test solutions for such unique defects; the approach will be illustrated for Stuck-at-Polarization (SAP) defects.

AB - As emerging non-volatile memory (NVM) devices, Ferroelectric Field-Effect Transistors (FeFETs) present distinctive opportunities for the design of ultra-dense and low-leakage memory systems. For matured FeFET manufacturing, it is extremely important to have an understanding of manufacturing defects and accurately model them to develop effective test solutions. This paper introduces a comprehensive framework for defect and fault modeling, which enables the development of test solutions. First, a classification of FeFET manufacturing defects is provided; both conventional defects (such as contacts and interconnect defects) as well as unique FeFET defects are discussed. The latter FeFET specific defect leads to unique faults that cannot be adequately described using traditional modeling approaches. Then, the Device-Aware Test (DAT) method is used to effectively and appropriately model, analyze and develop test solutions for such unique defects; the approach will be illustrated for Stuck-at-Polarization (SAP) defects.

KW - defect modeling

KW - device-aware defect model

KW - fault modeling

KW - fefet

KW - memory test

UR - http://www.scopus.com/inward/record.url?scp=85212975380&partnerID=8YFLogxK

U2 - 10.1109/ITC51657.2024.00026

DO - 10.1109/ITC51657.2024.00026

M3 - Conference contribution

AN - SCOPUS:85212975380

T3 - Proceedings - International Test Conference

SP - 91

EP - 95

BT - Proceedings - 2024 IEEE International Test Conference, ITC 2024

PB - IEEE

T2 - 2024 IEEE International Test Conference, ITC 2024

Y2 - 3 November 2024 through 8 November 2024

ER -

Defects, Fault Modeling, and Test Development Framework for FeFETs

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

Other files and links

Fingerprint

Cite this