Delamination Analysis of Cu/low-k Technology Subjected to Chemical-Mechanical Polishing Process Conditions

CA Yuan, WD van Driel, RBR van Silfhout, O van der Sluis, RAB Engelen, LJ Ernst, F van Keulen, GQ Zhang

Research output: Contribution to journalArticleScientific

8 Citations (Scopus)

Abstract

The mechanical response at the interface between the silicon, low-k and copper layer of the wafer is simulated herein under the loading of the chemical-mechanical polishing (CMP). To identify the possible generation/propagation of the initial crack, the warpage induced by the thin-film fabrication process are considered, and applying pressure, status of slurry and the copper thickness are treated as the parameter in the simulation. Both the simulation and experimental results indicate that the large blanket wafer within high applying pressure would exhibit high stresses possible to delaminate the interface at the periphery of the wafer, and reducing the copper thickness can diminish the possibility of the delamination/failure of the low-k material.
Original languageUndefined/Unknown
Pages (from-to)1679-1684
Number of pages6
JournalMicroelectronics Reliability
Volume46
Publication statusPublished - 2006

Keywords

  • academic journal papers
  • CWTS JFIS < 0.75

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