Delay evaluation of high speed data-path circuits based on threshold logic

P Celinski, D Abbott, SD Cotofana

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Original languageUndefined/Unknown
Title of host publicationIntegrated circuit and system design; Power and timing modeling, optimization and simulation
EditorsE Macii, V Paliouras, O Koufopavlou
Place of PublicationBerlin
PublisherSpringer
Pages899-906
Number of pages8
ISBN (Print)3-540-23095-5
Publication statusPublished - 2004
Event14th International Workshop, PATMOS, Santorini, Greece - Berlin
Duration: 15 Sep 200417 Sep 2004

Publication series

Name
PublisherSpringer-Verlag
NameLecture Notes in Computer Science
Volume3254
ISSN (Print)0302-9743

Conference

Conference14th International Workshop, PATMOS, Santorini, Greece
Period15/09/0417/09/04

Keywords

  • conference contrib. refereed
  • ZX CWTS JFIS < 1.00

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