Delay evaluation of high speed data-path circuits based on threshold logic

P Celinski; D Abbott; SD Cotofana

Delay evaluation of high speed data-path circuits based on threshold logic

P Celinski, D Abbott, SD Cotofana

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

Original language	Undefined/Unknown
Title of host publication	Integrated circuit and system design; Power and timing modeling, optimization and simulation
Editors	E Macii, V Paliouras, O Koufopavlou
Place of Publication	Berlin
Publisher	Springer
Pages	899-906
Number of pages	8
ISBN (Print)	3-540-23095-5
Publication status	Published - 2004
Event	14th International Workshop, PATMOS, Santorini, Greece - Berlin Duration: 15 Sept 2004 → 17 Sept 2004

Publication series

Name
Publisher	Springer-Verlag

Name	Lecture Notes in Computer Science
Volume	3254
ISSN (Print)	0302-9743

Conference

Conference	14th International Workshop, PATMOS, Santorini, Greece
Period	15/09/04 → 17/09/04

Keywords

conference contrib. refereed
ZX CWTS JFIS < 1.00

Cite this

@inproceedings{787c31aa09f340cca67b8585b4870867,

title = "Delay evaluation of high speed data-path circuits based on threshold logic",

keywords = "conference contrib. refereed, ZX CWTS JFIS < 1.00",

author = "P Celinski and D Abbott and SD Cotofana",

year = "2004",

language = "Undefined/Unknown",

isbn = "3-540-23095-5",

publisher = "Springer",

pages = "899--906",

editor = "E Macii and V Paliouras and O Koufopavlou",

booktitle = "Integrated circuit and system design; Power and timing modeling, optimization and simulation",

note = "14th International Workshop, PATMOS, Santorini, Greece ; Conference date: 15-09-2004 Through 17-09-2004",

}

Celinski, P, Abbott, D & Cotofana, SD 2004, Delay evaluation of high speed data-path circuits based on threshold logic. in E Macii, V Paliouras & O Koufopavlou (eds), Integrated circuit and system design; Power and timing modeling, optimization and simulation. Lecture Notes in Computer Science, vol. 3254, Springer, Berlin, pp. 899-906, 14th International Workshop, PATMOS, Santorini, Greece, 15/09/04.

Delay evaluation of high speed data-path circuits based on threshold logic. / Celinski, P; Abbott, D; Cotofana, SD.
Integrated circuit and system design; Power and timing modeling, optimization and simulation. ed. / E Macii; V Paliouras; O Koufopavlou. Berlin: Springer, 2004. p. 899-906 (Lecture Notes in Computer Science; Vol. 3254).

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Delay evaluation of high speed data-path circuits based on threshold logic

AU - Celinski, P

AU - Abbott, D

AU - Cotofana, SD

PY - 2004

Y1 - 2004

KW - conference contrib. refereed

KW - ZX CWTS JFIS < 1.00

M3 - Conference contribution

SN - 3-540-23095-5

SP - 899

EP - 906

BT - Integrated circuit and system design; Power and timing modeling, optimization and simulation

A2 - Macii, E

A2 - Paliouras, V

A2 - Koufopavlou, O

PB - Springer

CY - Berlin

T2 - 14th International Workshop, PATMOS, Santorini, Greece

Y2 - 15 September 2004 through 17 September 2004

ER -