Design and Analysis of PCB Embedded SiC Half-Bridge Packaging Cells with Low Thermal Resistance and Parasitic Inductance

Reducing parasitic parameters and thermal resistance is critical for advancing power electronic devices. This paper designs and evaluates the three Printed Circuit Board (PCB) embedded 1200 V SiC MOSFET half-bridge packaging cells, where the traditional wire bonding process is replaced by a re-distribution layer (RDL) technique. A comprehensive evaluation of their electrical performance, thermal management, and mechanical performance is conducted. The three solutions that employ panel, active metal brazing (AMB), and lead-frame carriers, are developed through a streamlined process that includes die attach, molding, drilling, plating, and etching. This packaging approach readily reduces the parasitic inductance to below 5 nH. By utilizing a single-layer RDL with mutual inductance cancellation, the power loop inductance is reduced to as low as 2.4 nH (at 10 MHz), and the gate loop inductance to 1.57 nH (at 10 MHz). The junction-to-case thermal resistances of the three solutions are 1.88 K/W, 1.03 K/W, and 0.73 K/W, respectively. Compared with the other two packaging cells, the cell selecting AMB as a carrier reduces SiC MOSFET operational stress and deformation by approximately 34% and 75%. The lead- frame carrier offers superior thermal dissipation for potential TO package replacement in half-bridge topologies, while the panel solution is promising for dual-sided cooling applications. With low thermal resistance, minimal stress, and excellent backside electrical insulation, the packaging cell with an AMB carrier is ideally suited for integration with heatsinks in traction inverters.