Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs

P Chen; X Huang; YH Liu; M Ding; C Zhou; A Ba; K Philips; H de Groot; RB Staszewski

doi:10.1109/ESSCIRC.2015.7313882

Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs

P Chen^*, X Huang, YH Liu, M Ding, C Zhou, A Ba, K Philips, H de Groot, RB Staszewski

^*Corresponding author for this work

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

10 Citations (Scopus)

Original language	English
Title of host publication	Proceedings of the 41st European solid-state circuits conference, ESSCIRC 2015
Editors	W Pribyl, F Dielacher, G Hueber
Place of Publication	Piscataway
Publisher	IEEE
Pages	283-286
Number of pages	4
ISBN (Print)	978-1-4673-7470-5
DOIs	https://doi.org/10.1109/ESSCIRC.2015.7313882
Publication status	Published - 2015
Externally published	Yes
Event	ESSCIRC 2015: 41th European Solid-State Circuits Conference - Messe Congress, Graz, Austria Duration: 14 Sept 2015 → 18 Sept 2015 Conference number: 41

Conference

Conference	ESSCIRC 2015
Abbreviated title	ESSCIRC
Country/Territory	Austria
City	Graz
Period	14/09/15 → 18/09/15

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10.1109/ESSCIRC.2015.7313882

Cite this

Chen, P., Huang, X., Liu, YH., Ding, M., Zhou, C., Ba, A., Philips, K., de Groot, H., & Staszewski, RB. (2015). Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs. In W. Pribyl, F. Dielacher, & G. Hueber (Eds.), Proceedings of the 41st European solid-state circuits conference, ESSCIRC 2015 (pp. 283-286). IEEE. https://doi.org/10.1109/ESSCIRC.2015.7313882

@inproceedings{474a6f58994846efbd18c76b70b21e48,

title = "Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs",

author = "P Chen and X Huang and YH Liu and M Ding and C Zhou and A Ba and K Philips and \{de Groot\}, H and RB Staszewski",

year = "2015",

doi = "10.1109/ESSCIRC.2015.7313882",

language = "English",

isbn = "978-1-4673-7470-5",

pages = "283--286",

editor = "W Pribyl and F Dielacher and G Hueber",

booktitle = "Proceedings of the 41st European solid-state circuits conference, ESSCIRC 2015",

publisher = "IEEE",

address = "United States",

note = "ESSCIRC 2015 : 41th European Solid-State Circuits Conference, ESSCIRC ; Conference date: 14-09-2015 Through 18-09-2015",

}

Chen, P, Huang, X, Liu, YH, Ding, M, Zhou, C, Ba, A, Philips, K, de Groot, H & Staszewski, RB 2015, Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs. in W Pribyl, F Dielacher & G Hueber (eds), Proceedings of the 41st European solid-state circuits conference, ESSCIRC 2015. IEEE, Piscataway, pp. 283-286, ESSCIRC 2015, Graz, Austria, 14/09/15. https://doi.org/10.1109/ESSCIRC.2015.7313882

Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs. / Chen, P; Huang, X; Liu, YH et al.
Proceedings of the 41st European solid-state circuits conference, ESSCIRC 2015. ed. / W Pribyl; F Dielacher; G Hueber. Piscataway: IEEE, 2015. p. 283-286.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs

AU - Chen, P

AU - Huang, X

AU - Liu, YH

AU - Ding, M

AU - Zhou, C

AU - Ba, A

AU - Philips, K

AU - de Groot, H

AU - Staszewski, RB

N1 - Conference code: 41

PY - 2015

Y1 - 2015

UR - https://www.scopus.com/pages/publications/84958761102

U2 - 10.1109/ESSCIRC.2015.7313882

DO - 10.1109/ESSCIRC.2015.7313882

M3 - Conference contribution

SN - 978-1-4673-7470-5

SP - 283

EP - 286

BT - Proceedings of the 41st European solid-state circuits conference, ESSCIRC 2015

A2 - Pribyl, W

A2 - Dielacher, F

A2 - Hueber, G

PB - IEEE

CY - Piscataway

T2 - ESSCIRC 2015

Y2 - 14 September 2015 through 18 September 2015

ER -

Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs

Conference

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