Design and Qualification of a High-Speed Low-Power Comparator in 40 nm CMOS Technology

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Abstract

This paper presents the design methodology, test setup and experimental qualification results of a high-speed low-power threshold comparator in 40 nm CMOS technology intended for the registry of particles landing on a PIN-detector surface in particle detector readout electronics. The operation of the designed comparator is experimentally qualified for ideal digital pulses and analog signals generated by the preceding stages in a targeted potential application.
Original languageEnglish
Title of host publication2023 32nd International Scientific Conference Electronics, ET 2023 - Proceedings
PublisherIEEE
Pages1-5
Number of pages5
ISBN (Electronic)979-8-3503-0200-4
ISBN (Print)979-8-3503-0201-1
DOIs
Publication statusPublished - 2023
Event2023 XXXII International Scientific Conference Electronics (ET) - Sozopol, Bulgaria
Duration: 13 Sept 202315 Sept 2023

Publication series

Name2023 32nd International Scientific Conference Electronics, ET 2023 - Proceedings

Conference

Conference2023 XXXII International Scientific Conference Electronics (ET)
Country/TerritoryBulgaria
CitySozopol
Period13/09/2315/09/23

Bibliographical note

Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Keywords

  • high-speed
  • low-power
  • readout interface
  • voltage comparator
  • temperature sensor

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