Design of a pipelined and parameterized VLIW processor: r-VEX v.2.0

RAE Seedorf, F Anjam, AAC Brandon, JSSM Wong

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

Original language	English
Title of host publication	6th HiPEAC workshop on reconfigurable computing
Editors	s.n.
Place of Publication	s.l.
Publisher	s.n.
Pages	1-12
Number of pages	12
Publication status	Published - 2012
Event	WRC 2012 - s.l. Duration: 24 Jan 2012 → 24 Jan 2012

Name
Publisher	s.n.

Conference	WRC 2012
Period	24/01/12 → 24/01/12

Cite this

@inproceedings{d97bf68b669143ab824cad05128d21e7,

title = "Design of a pipelined and parameterized VLIW processor: r-VEX v.2.0",

author = "RAE Seedorf and F Anjam and AAC Brandon and JSSM Wong",

year = "2012",

language = "English",

publisher = "s.n.",

pages = "1--12",

editor = "s.n.",

booktitle = "6th HiPEAC workshop on reconfigurable computing",

note = "WRC 2012 ; Conference date: 24-01-2012 Through 24-01-2012",

}