Wafer Level Packages are one of the most advanced packaging concepts. It combines the advantages of flip chip with conventional surface mount technologies. In recent years, we have seen a tremendous growth in the application of Wafer Level Packages, both in quantities as well as in the number of products where they are implemented. The technology is, however, not without its challenges with 1st and 2nd level reliability issues. For instance, the limit on the size of Wafer Level Packages has to do with the 2nd level, or solder bump, reliability. This paper highlights our major research and development results on understanding and enhancing the 1st and 2nd level reliability of Wafer Level Packages using combined experimental and virtual prototyping (thermal, mechanical and thermo-mechanical) techniques. Typical 1st level reliability problems within Wafer Level Packages are cracking of repassivation materials, fatigue of bond over active pads, and cracks within the Under Bump Metalisation. Typical 2nd level problems concern solder fatigue and brittle fractures within the intermetallics. To investigate the physics of failure for these problems, dedicated parametric finite element models are constructed including the thin IC layers. Two structures are explored to their potential reliability benefits, being the traditionally used repassivation structure and a newly developed Bump on Active structure. This so-called BUMA structure makes use of a thick A1 buffer layer. By combining the experimental results with reliability prediction models, both structures in terms of 1st and 2ne level reliability performance are explored. Based on the results we have designed and manufactured an improved construction that significantly outperforms current solutions.
|Number of pages||8|
|Publication status||Published - 2010|
- academic journal papers
- CWTS JFIS < 0.75