Development of a DRAM simulation model for fault analysis purposes

Z Al-Ars, A Zaid, AJ van de Goor, B Gauch, D Richter, W Spirkl

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific

Original language	Undefined/Unknown
Title of host publication	Proceedings
Place of Publication	S.l.
Publisher	s.n.
Pages	1-4
Number of pages	4
Publication status	Published - 2001
Event	13th Workshop Testmethods and Reliability of Circuits and Systems, Miesbach - S.l. Duration: 18 Feb 2001 → 20 Feb 2001

Name
Publisher	S.n.

Conference	13th Workshop Testmethods and Reliability of Circuits and Systems, Miesbach
Period	18/02/01 → 20/02/01

Keywords

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title = "Development of a DRAM simulation model for fault analysis purposes",

keywords = "ZX Int.klas.verslagjaar < 2002",

author = "Z Al-Ars and A Zaid and {van de Goor}, AJ and B Gauch and D Richter and W Spirkl",

year = "2001",

language = "Undefined/Unknown",

publisher = "s.n.",

pages = "1--4",

booktitle = "Proceedings",

note = "13th Workshop Testmethods and Reliability of Circuits and Systems, Miesbach ; Conference date: 18-02-2001 Through 20-02-2001",

}

TY - GEN

T1 - Development of a DRAM simulation model for fault analysis purposes

AU - Al-Ars, Z

AU - Zaid, A

AU - van de Goor, AJ

AU - Gauch, B

AU - Richter, D

AU - Spirkl, W

PY - 2001

Y1 - 2001

KW - ZX Int.klas.verslagjaar < 2002

M3 - Conference contribution

SP - 1

EP - 4

BT - Proceedings

PB - s.n.

CY - S.l.

T2 - 13th Workshop Testmethods and Reliability of Circuits and Systems, Miesbach

Y2 - 18 February 2001 through 20 February 2001

ER -