Device-Aware Test: A New Test Approach Towards DPPB Level

M. Fieback, Lizhou Wu, Guilherme Cardoso Medeiros, Hassen Aziza, S Rao, Erik Jan Marinissen, Mottaqiallah Taouil, Said Hamdioui

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

8 Citations (Scopus)
65 Downloads (Pure)

Abstract

This paper proposes a new test approach that goes beyond cell-aware test, i.e., device-aware test. The approach consists of three steps: defect modeling, fault modeling, and test/DfT development. The defect modeling does not assume that a defect in a device (or a cell) can be modeled electrically as a linear resistor (as the traditional approach suggests), but it rather incorporates the impact of the physical defect on the technology parameters of the device and thereafter on its electrical parameters. Once the defective electrical model is defined, a systematic fault analysis (based on fault simulation) is performed to derive appropriate fault models and subsequently test solutions. The approach is demonstrated using two memory technologies: resistive random access memory (RRAM) and spin-transfer torque magnetic random access memory (STT-MRAM). The results show that the proposed approach is able to sensitize faults for defects that are not detected with the traditional approach, meaning that the latter cannot lead to high-quality test solutions as required for a defective part per billion (DPPB) level. The new approach clearly sets up a turning point in testing for at least the considered two emerging memory technologies.
Original languageEnglish
Title of host publication2019 IEEE International Test Conference, ITC 2019
PublisherIEEE
Number of pages10
ISBN (Electronic)978-1-7281-4823-6
ISBN (Print)978-1-7281-4824-3
DOIs
Publication statusPublished - 9 Nov 2019

Publication series

NameProceedings - International Test Conference
Volume2019-November
ISSN (Print)1089-3539

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