DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs

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Abstract

Hard-to-detect faults such as weak and random faults in FinFET SRAMs represent an important challenge for manufacturing testing in scaled technologies, as they may lead to test escapes. This paper proposes a Design-for-Testability (DFT) scheme able to detect such faults by monitoring the bitline swing of FinFET memories. Using only five operations per cell, we are able to detect defects that cause deterministic, random, and weak faults. Compared to the state of the art, this leads to an improved detection capability at reduced area overhead.
Original languageEnglish
Title of host publicationProceedings - 2019 IEEE European Test Symposium, ETS 2019
Subtitle of host publicationProceedings
PublisherIEEE
Pages1-2
Number of pages2
Volume2019-May
ISBN (Electronic) 978-1-7281-1173-5
ISBN (Print)978-1-7281-1174-2
DOIs
Publication statusPublished - 2019
Event24th IEEE European Test Symposium 2019 - Baden-Baden, Germany
Duration: 27 May 201931 May 2019
Conference number: 24th
http://www.testgroup.polito.it/ets19

Conference

Conference24th IEEE European Test Symposium 2019
Abbreviated titleETS
CountryGermany
CityBaden-Baden
Period27/05/1931/05/19
Internet address

Keywords

  • Hard-to-Detect Faults
  • DFT
  • SRAM
  • FinFET

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  • Cite this

    Cardoso Medeiros, G., Taouil, M., Fieback, M., Bolzani Poehls, L. M., & Hamdioui, S. (2019). DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs. In Proceedings - 2019 IEEE European Test Symposium, ETS 2019: Proceedings (Vol. 2019-May, pp. 1-2). [8791517] IEEE. https://doi.org/10.1109/ETS.2019.8791517