DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs

Guilherme Cardoso Medeiros; Mottaqiallah Taouil; Moritz Fieback; L. M. Bolzani Poehls; Said Hamdioui

doi:10.1109/ETS.2019.8791517

DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs

Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Moritz Fieback, L. M. Bolzani Poehls, Said Hamdioui

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

11 Citations (Scopus)

282 Downloads (Pure)

Abstract

Hard-to-detect faults such as weak and random faults in FinFET SRAMs represent an important challenge for manufacturing testing in scaled technologies, as they may lead to test escapes. This paper proposes a Design-for-Testability (DFT) scheme able to detect such faults by monitoring the bitline swing of FinFET memories. Using only five operations per cell, we are able to detect defects that cause deterministic, random, and weak faults. Compared to the state of the art, this leads to an improved detection capability at reduced area overhead.

Original language	English
Title of host publication	Proceedings - 2019 IEEE European Test Symposium, ETS 2019
Subtitle of host publication	Proceedings
Publisher	IEEE
Pages	1-2
Number of pages	2
Volume	2019-May
ISBN (Electronic)	978-1-7281-1173-5
ISBN (Print)	978-1-7281-1174-2
DOIs	https://doi.org/10.1109/ETS.2019.8791517
Publication status	Published - 2019
Event	24th IEEE European Test Symposium 2019 - Baden-Baden, Germany Duration: 27 May 2019 → 31 May 2019 Conference number: 24th http://www.testgroup.polito.it/ets19

Conference

Conference	24th IEEE European Test Symposium 2019
Abbreviated title	ETS
Country/Territory	Germany
City	Baden-Baden
Period	27/05/19 → 31/05/19
Internet address	http://www.testgroup.polito.it/ets19

Bibliographical note

Accepted author manuscript

Keywords

Hard-to-Detect Faults
DFT
SRAM
FinFET

Access to Document

10.1109/ETS.2019.8791517

ETS19Accepted author manuscript, 1.07 MB

Cite this

@inproceedings{e84033f1326d4576a2b72ef8088657c6,

title = "DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs",

abstract = "Hard-to-detect faults such as weak and random faults in FinFET SRAMs represent an important challenge for manufacturing testing in scaled technologies, as they may lead to test escapes. This paper proposes a Design-for-Testability (DFT) scheme able to detect such faults by monitoring the bitline swing of FinFET memories. Using only five operations per cell, we are able to detect defects that cause deterministic, random, and weak faults. Compared to the state of the art, this leads to an improved detection capability at reduced area overhead.",

keywords = "Hard-to-Detect Faults, DFT, SRAM, FinFET",

author = "\{Cardoso Medeiros\}, Guilherme and Mottaqiallah Taouil and Moritz Fieback and \{Bolzani Poehls\}, \{L. M.\} and Said Hamdioui",

note = "Accepted author manuscript; 24th IEEE European Test Symposium 2019, ETS ; Conference date: 27-05-2019 Through 31-05-2019",

year = "2019",

doi = "10.1109/ETS.2019.8791517",

language = "English",

isbn = "978-1-7281-1174-2",

volume = "2019-May",

pages = "1--2",

booktitle = "Proceedings - 2019 IEEE European Test Symposium, ETS 2019",

publisher = "IEEE",

address = "United States",

url = "http://www.testgroup.polito.it/ets19",

}

DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs. / Cardoso Medeiros, Guilherme; Taouil, Mottaqiallah ; Fieback, Moritz et al.
Proceedings - 2019 IEEE European Test Symposium, ETS 2019: Proceedings. Vol. 2019-May IEEE, 2019. p. 1-2 8791517.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs

AU - Cardoso Medeiros, Guilherme

AU - Taouil, Mottaqiallah

AU - Fieback, Moritz

AU - Bolzani Poehls, L. M.

AU - Hamdioui, Said

N1 - Conference code: 24th

PY - 2019

Y1 - 2019

N2 - Hard-to-detect faults such as weak and random faults in FinFET SRAMs represent an important challenge for manufacturing testing in scaled technologies, as they may lead to test escapes. This paper proposes a Design-for-Testability (DFT) scheme able to detect such faults by monitoring the bitline swing of FinFET memories. Using only five operations per cell, we are able to detect defects that cause deterministic, random, and weak faults. Compared to the state of the art, this leads to an improved detection capability at reduced area overhead.

AB - Hard-to-detect faults such as weak and random faults in FinFET SRAMs represent an important challenge for manufacturing testing in scaled technologies, as they may lead to test escapes. This paper proposes a Design-for-Testability (DFT) scheme able to detect such faults by monitoring the bitline swing of FinFET memories. Using only five operations per cell, we are able to detect defects that cause deterministic, random, and weak faults. Compared to the state of the art, this leads to an improved detection capability at reduced area overhead.

KW - Hard-to-Detect Faults

KW - DFT

KW - SRAM

KW - FinFET

UR - https://www.scopus.com/pages/publications/85071180665

U2 - 10.1109/ETS.2019.8791517

DO - 10.1109/ETS.2019.8791517

M3 - Conference contribution

SN - 978-1-7281-1174-2

VL - 2019-May

SP - 1

EP - 2

BT - Proceedings - 2019 IEEE European Test Symposium, ETS 2019

PB - IEEE

T2 - 24th IEEE European Test Symposium 2019

Y2 - 27 May 2019 through 31 May 2019

ER -

DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs

Abstract

Conference

Bibliographical note

Keywords

Access to Document

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