Digital Spiking Neuron Cells for Real-Time Reconfigurable Learning Networks

Haipeng Lin; Amir Zjajo; Rene van Leuken

doi:10.1109/SOCC.2017.8226029

Digital Spiking Neuron Cells for Real-Time Reconfigurable Learning Networks

Haipeng Lin, Amir Zjajo, Rene van Leuken

Signal Processing Systems

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

1 Citation (Scopus)

Abstract

The high level of realism of spiking neuron networks and their complexity require a substantial computational resources limiting the size of the realized networks. Consequently, the main challenge in building complex and biologically-accurate spiking neuron network is largely set by the high computational and data transfer demands. In this paper, we implement several efficient models of the spiking neurons with characteristics such as axon conduction delays and spike timing-dependent plasticity. Experimental results indicate that the proposed real-time data-flow learning network architecture allows the capacity of over 2800 (depending on the model complexity) biophysically accurate neurons in a single FPGA device.

Original language	English
Title of host publication	Proceedings - 30th IEEE International System on Chip Conference, SOCC 2017
Editors	M. Alioto, H. Li, J. Becker, U. Schlichtmann, R. Sridhar
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	163-168
Number of pages	6
ISBN (Electronic)	978-1-5386-4034-0
ISBN (Print)	978-1-5386-4035-7
DOIs	https://doi.org/10.1109/SOCC.2017.8226029
Publication status	Published - 2017
Event	SOCC 2017: 30th IEEE International System on Chip Conference (SOCC) - Hotel Novotel , Munich, Germany Duration: 5 Aug 2017 → 8 Sept 2017 Conference number: 30

Conference

Conference	SOCC 2017
Country/Territory	Germany
City	Munich
Period	5/08/17 → 8/09/17

Keywords

Digital spiking neuron cells
neuron network
learning network
real-time data-flow architecture

Access to Document

10.1109/SOCC.2017.8226029

Cite this

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title = "Digital Spiking Neuron Cells for Real-Time Reconfigurable Learning Networks",

abstract = "The high level of realism of spiking neuron networks and their complexity require a substantial computational resources limiting the size of the realized networks. Consequently, the main challenge in building complex and biologically-accurate spiking neuron network is largely set by the high computational and data transfer demands. In this paper, we implement several efficient models of the spiking neurons with characteristics such as axon conduction delays and spike timing-dependent plasticity. Experimental results indicate that the proposed real-time data-flow learning network architecture allows the capacity of over 2800 (depending on the model complexity) biophysically accurate neurons in a single FPGA device.",

keywords = "Digital spiking neuron cells, neuron network, learning network, real-time data-flow architecture",

author = "Haipeng Lin and Amir Zjajo and {van Leuken}, Rene",

year = "2017",

doi = "10.1109/SOCC.2017.8226029",

language = "English",

isbn = "978-1-5386-4035-7",

pages = "163--168",

editor = "M. Alioto and H. Li and J. Becker and U. Schlichtmann and R. Sridhar",

booktitle = "Proceedings - 30th IEEE International System on Chip Conference, SOCC 2017",

publisher = "IEEE",

address = "United States",

note = "SOCC 2017 : 30th IEEE International System on Chip Conference (SOCC) ; Conference date: 05-08-2017 Through 08-09-2017",

}

Digital Spiking Neuron Cells for Real-Time Reconfigurable Learning Networks. / Lin, Haipeng; Zjajo, Amir; van Leuken, Rene.
Proceedings - 30th IEEE International System on Chip Conference, SOCC 2017. ed. / M. Alioto; H. Li; J. Becker; U. Schlichtmann; R. Sridhar. Piscataway, NJ: IEEE, 2017. p. 163-168.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Digital Spiking Neuron Cells for Real-Time Reconfigurable Learning Networks

AU - Lin, Haipeng

AU - Zjajo, Amir

AU - van Leuken, Rene

N1 - Conference code: 30

PY - 2017

Y1 - 2017

N2 - The high level of realism of spiking neuron networks and their complexity require a substantial computational resources limiting the size of the realized networks. Consequently, the main challenge in building complex and biologically-accurate spiking neuron network is largely set by the high computational and data transfer demands. In this paper, we implement several efficient models of the spiking neurons with characteristics such as axon conduction delays and spike timing-dependent plasticity. Experimental results indicate that the proposed real-time data-flow learning network architecture allows the capacity of over 2800 (depending on the model complexity) biophysically accurate neurons in a single FPGA device.

AB - The high level of realism of spiking neuron networks and their complexity require a substantial computational resources limiting the size of the realized networks. Consequently, the main challenge in building complex and biologically-accurate spiking neuron network is largely set by the high computational and data transfer demands. In this paper, we implement several efficient models of the spiking neurons with characteristics such as axon conduction delays and spike timing-dependent plasticity. Experimental results indicate that the proposed real-time data-flow learning network architecture allows the capacity of over 2800 (depending on the model complexity) biophysically accurate neurons in a single FPGA device.

KW - Digital spiking neuron cells

KW - neuron network

KW - learning network

KW - real-time data-flow architecture

U2 - 10.1109/SOCC.2017.8226029

DO - 10.1109/SOCC.2017.8226029

M3 - Conference contribution

SN - 978-1-5386-4035-7

SP - 163

EP - 168

BT - Proceedings - 30th IEEE International System on Chip Conference, SOCC 2017

A2 - Alioto, M.

A2 - Li, H.

A2 - Becker, J.

A2 - Schlichtmann, U.

A2 - Sridhar, R.

PB - IEEE

CY - Piscataway, NJ

T2 - SOCC 2017

Y2 - 5 August 2017 through 8 September 2017

ER -

Digital Spiking Neuron Cells for Real-Time Reconfigurable Learning Networks

Abstract

Conference

Keywords

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