DRAM fault analysis and test generation

Abstract Dynamic random access memories (DRAMs) are the most widelyused type of memory in the market today, due to theirimportant application as the main memory of the personalcomputer (PC). These memories are tested by theirmanufacturers in an ad hoc way, that results in anexpensive test process the price of which is ultimatelypaid by the end consumer.In this PhD dissertation, we propose a new alternativeapproach to the development of industrial memory testingthat is more systematic and less expensive than thecurrently used test approaches. The new approach is basedon the introduction of a number of fault analysisalgorithms that enable using electrical Spice simulationsto develop effective memory tests in a short amount of time.The new approach makes it possible to enhance memory testsin many different manufacturing stages, starting from theinitial test application stage where silicon ismanufactured, through the memory ramp-up stage whereproducts are shipped to the customer, and ending with thetest adaptation stage, based on memory failures in thefield. The new test development approach has beenimplemented and evaluated at Infineon Technologies, aleading DRAM manufacturer based in Germany, to developtests for their DRAM products.