Efficient On-line Testing Of An Array Of Reconfigurable Risc Processors

S. Pagliarini; S. Pontarelli; J. Mathew; D.K. Pradhan; I. Sourdis; D.A. Khan; A. Malek; S. Tzilis; G. Smaragdos; C. Strydis

Efficient On-line Testing Of An Array Of Reconfigurable Risc Processors

S. Pagliarini, S. Pontarelli, J. Mathew, D.K. Pradhan, I. Sourdis, D.A. Khan, A. Malek, S. Tzilis, G. Smaragdos, C. Strydis

Research output: Chapter in Book/Conference proceedings/Edited volume › Chapter › Scientific › peer-review

Abstract

This paper presents an efficient method for testing an array of reconfigurable RISC processors. The online testing method exploits the reconfiguration capabilities of the array to detect permanent faults and to identify which component of the RISC processors is affected by a fault. Based on a low cost hardware scheme, several testing procedures have been developed, that are able to locate the faulty unit in different operating conditions.

Original language	English
Title of host publication	4th MEDIAN Workshop
Place of Publication	Grenoble, France
Publisher	MEDIAN
Pages	52-55
Number of pages	4
Publication status	Published - 2015
Externally published	Yes
Event	4th MEDIAN Workshop - Duration: 1 Jan 2015 → 1 Jan 2015 Conference number: 4

Workshop

Workshop	4th MEDIAN Workshop
Period	1/01/15 → 1/01/15

Cite this

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title = "Efficient On-line Testing Of An Array Of Reconfigurable Risc Processors",

abstract = "This paper presents an efficient method for testing an array of reconfigurable RISC processors. The online testing method exploits the reconfiguration capabilities of the array to detect permanent faults and to identify which component of the RISC processors is affected by a fault. Based on a low cost hardware scheme, several testing procedures have been developed, that are able to locate the faulty unit in different operating conditions.",

author = "S. Pagliarini and S. Pontarelli and J. Mathew and D.K. Pradhan and I. Sourdis and D.A. Khan and A. Malek and S. Tzilis and G. Smaragdos and C. Strydis",

year = "2015",

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note = "4th MEDIAN Workshop ; Conference date: 01-01-2015 Through 01-01-2015",

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TY - CHAP

T1 - Efficient On-line Testing Of An Array Of Reconfigurable Risc Processors

AU - Pagliarini, S.

AU - Pontarelli, S.

AU - Mathew, J.

AU - Pradhan, D.K.

AU - Sourdis, I.

AU - Khan, D.A.

AU - Malek, A.

AU - Tzilis, S.

AU - Smaragdos, G.

AU - Strydis, C.

N1 - Conference code: 4

PY - 2015

Y1 - 2015

N2 - This paper presents an efficient method for testing an array of reconfigurable RISC processors. The online testing method exploits the reconfiguration capabilities of the array to detect permanent faults and to identify which component of the RISC processors is affected by a fault. Based on a low cost hardware scheme, several testing procedures have been developed, that are able to locate the faulty unit in different operating conditions.

AB - This paper presents an efficient method for testing an array of reconfigurable RISC processors. The online testing method exploits the reconfiguration capabilities of the array to detect permanent faults and to identify which component of the RISC processors is affected by a fault. Based on a low cost hardware scheme, several testing procedures have been developed, that are able to locate the faulty unit in different operating conditions.

M3 - Chapter

SP - 52

EP - 55

BT - 4th MEDIAN Workshop

PB - MEDIAN

CY - Grenoble, France

T2 - 4th MEDIAN Workshop

Y2 - 1 January 2015 through 1 January 2015

ER -

Efficient On-line Testing Of An Array Of Reconfigurable Risc Processors

Abstract

Workshop

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