Efficient On-line Testing Of An Array Of Reconfigurable Risc Processors

S. Pagliarini, S. Pontarelli, J. Mathew, D.K. Pradhan, I. Sourdis, D.A. Khan, A. Malek, S. Tzilis, G. Smaragdos, C. Strydis

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review


This paper presents an efficient method for testing an array of reconfigurable RISC processors. The online testing method exploits the reconfiguration capabilities of the array to detect permanent faults and to identify which component of the RISC processors is affected by a fault. Based on a low cost hardware scheme, several testing procedures have been developed, that are able to locate the faulty unit in different operating conditions.
Original languageEnglish
Title of host publication4th MEDIAN Workshop
Place of PublicationGrenoble, France
Number of pages4
Publication statusPublished - 2015
Externally publishedYes
Event4th MEDIAN Workshop -
Duration: 1 Jan 20151 Jan 2015
Conference number: 4


Workshop4th MEDIAN Workshop


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