Energy-Efficient SNN Implementation Using RRAM-Based Computation In-Memory (CIM)

Asmae El Arrassi; Anteneh Gebregiorgis; Anass El  Haddadi; Said Hamdioui

doi:10.1109/VLSI-SoC54400.2022.9939654

Energy-Efficient SNN Implementation Using RRAM-Based Computation In-Memory (CIM)

Asmae El Arrassi^*, Anteneh Gebregiorgis, Anass El Haddadi^*, Said Hamdioui

^*Corresponding author for this work

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

4 Citations (Scopus)

32 Downloads (Pure)

Abstract

Spiking Neural Networks (SNNs) can drastically improve the energy efficiency of neuromorphic computing through network sparsity and event-driven execution. Thus, SNNs have the potential to support practical cognitive tasks on resource constrained platforms, such as edge devices. To realize this, SNN requires energy-efficient hardware which can run applications with a limited energy budget. However, the conventional CMOS implementations cannot achieve this goal due to the various architectural and technological challenges. In this work, we address these issues by developing an energy-efficient and accurate SNN hardware based on Computation In-Memory (CIM) architecture using Resistive Random Access Memory (RRAM) devices. The developed SNN architecture is based on unsupervised Spike Time Dependent Plasticity (STDP) learning algorithm with online learning capability. Simulation results show that the proposed architecture is energy-efficient with a consumption of ≈20 fJ per spike, while maintaining state-of-the-art inference accuracy of 95% when evaluated using the MNIST dataset.

Original language	English
Title of host publication	Proceedings of the 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)
Publisher	IEEE
Pages	1-6
Number of pages	6
ISBN (Electronic)	978-1-6654-9005-4
ISBN (Print)	978-1-6654-9006-1
DOIs	https://doi.org/10.1109/VLSI-SoC54400.2022.9939654
Publication status	Published - 2022
Event	2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC) - Patras, Greece Duration: 3 Oct 2022 → 5 Oct 2022

Conference

Conference	2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)
Country/Territory	Greece
City	Patras
Period	3/10/22 → 5/10/22

Bibliographical note

Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care

Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Keywords

SNN
RRAM
In-Memory Computing
STDP

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/VLSI-SoC54400.2022.9939654

Energy-Efficient_SNN_Implementation_Using_RRAM-Based_Computation_In-Memory_CIMFinal published version, 3.02 MB

Cite this

@inproceedings{8fc5e8071ccd4593b0175c7847ae0cbf,

title = "Energy-Efficient SNN Implementation Using RRAM-Based Computation In-Memory (CIM)",

abstract = "Spiking Neural Networks (SNNs) can drastically improve the energy efficiency of neuromorphic computing through network sparsity and event-driven execution. Thus, SNNs have the potential to support practical cognitive tasks on resource constrained platforms, such as edge devices. To realize this, SNN requires energy-efficient hardware which can run applications with a limited energy budget. However, the conventional CMOS implementations cannot achieve this goal due to the various architectural and technological challenges. In this work, we address these issues by developing an energy-efficient and accurate SNN hardware based on Computation In-Memory (CIM) architecture using Resistive Random Access Memory (RRAM) devices. The developed SNN architecture is based on unsupervised Spike Time Dependent Plasticity (STDP) learning algorithm with online learning capability. Simulation results show that the proposed architecture is energy-efficient with a consumption of ≈20 fJ per spike, while maintaining state-of-the-art inference accuracy of 95% when evaluated using the MNIST dataset.",

keywords = "SNN, RRAM, In-Memory Computing, STDP",

author = "{El Arrassi}, Asmae and Anteneh Gebregiorgis and Haddadi, {Anass El} and Said Hamdioui",

note = "Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.; 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC) ; Conference date: 03-10-2022 Through 05-10-2022",

year = "2022",

doi = "10.1109/VLSI-SoC54400.2022.9939654",

language = "English",

isbn = "978-1-6654-9006-1",

pages = "1--6",

booktitle = "Proceedings of the 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)",

publisher = "IEEE",

address = "United States",

}

El Arrassi, A , Gebregiorgis, A, Haddadi, AE & Hamdioui, S 2022, Energy-Efficient SNN Implementation Using RRAM-Based Computation In-Memory (CIM). in Proceedings of the 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, pp. 1-6, 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC), Patras, Greece, 3/10/22. https://doi.org/10.1109/VLSI-SoC54400.2022.9939654

Energy-Efficient SNN Implementation Using RRAM-Based Computation In-Memory (CIM). / El Arrassi, Asmae ; Gebregiorgis, Anteneh; Haddadi, Anass El et al.
Proceedings of the 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2022. p. 1-6.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Energy-Efficient SNN Implementation Using RRAM-Based Computation In-Memory (CIM)

AU - El Arrassi, Asmae

AU - Gebregiorgis, Anteneh

AU - Haddadi, Anass El

AU - Hamdioui, Said

N1 - Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

PY - 2022

Y1 - 2022

N2 - Spiking Neural Networks (SNNs) can drastically improve the energy efficiency of neuromorphic computing through network sparsity and event-driven execution. Thus, SNNs have the potential to support practical cognitive tasks on resource constrained platforms, such as edge devices. To realize this, SNN requires energy-efficient hardware which can run applications with a limited energy budget. However, the conventional CMOS implementations cannot achieve this goal due to the various architectural and technological challenges. In this work, we address these issues by developing an energy-efficient and accurate SNN hardware based on Computation In-Memory (CIM) architecture using Resistive Random Access Memory (RRAM) devices. The developed SNN architecture is based on unsupervised Spike Time Dependent Plasticity (STDP) learning algorithm with online learning capability. Simulation results show that the proposed architecture is energy-efficient with a consumption of ≈20 fJ per spike, while maintaining state-of-the-art inference accuracy of 95% when evaluated using the MNIST dataset.

AB - Spiking Neural Networks (SNNs) can drastically improve the energy efficiency of neuromorphic computing through network sparsity and event-driven execution. Thus, SNNs have the potential to support practical cognitive tasks on resource constrained platforms, such as edge devices. To realize this, SNN requires energy-efficient hardware which can run applications with a limited energy budget. However, the conventional CMOS implementations cannot achieve this goal due to the various architectural and technological challenges. In this work, we address these issues by developing an energy-efficient and accurate SNN hardware based on Computation In-Memory (CIM) architecture using Resistive Random Access Memory (RRAM) devices. The developed SNN architecture is based on unsupervised Spike Time Dependent Plasticity (STDP) learning algorithm with online learning capability. Simulation results show that the proposed architecture is energy-efficient with a consumption of ≈20 fJ per spike, while maintaining state-of-the-art inference accuracy of 95% when evaluated using the MNIST dataset.

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KW - In-Memory Computing

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U2 - 10.1109/VLSI-SoC54400.2022.9939654

DO - 10.1109/VLSI-SoC54400.2022.9939654

M3 - Conference contribution

SN - 978-1-6654-9006-1

SP - 1

EP - 6

BT - Proceedings of the 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)

PB - IEEE

T2 - 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)

Y2 - 3 October 2022 through 5 October 2022

ER -

Energy-Efficient SNN Implementation Using RRAM-Based Computation In-Memory (CIM)

Abstract

Conference

Bibliographical note

Keywords

UN SDGs

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