ESRAM Reliability: Why is it still not optimally solved?

Daniel Kraak; Mottaqiallah Taouil; Said Hamdioui; Pieter Weckx; Stefan Cosemans; Francky Catthoor

doi:10.1109/DTIS48698.2020.9081145

ESRAM Reliability: Why is it still not optimally solved?

Daniel Kraak, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

1 Citation (Scopus)

Abstract

As technology scales down, the impact of variability due to process variation and aging increases. In order to guarantee an optimal design with a low failure rate, it is crucial to take into account the impact of these sources of variability. Prior work on SRAM reliability has mainly focused on estimating the impact of this variability on the memory cell array, while the peripheral circuitry and the complete memory circuit have received little attention. This study analyzes the impact of aging on a complete 14nm FinFET SRAM circuit. In this analysis, it is investigated how the memory's individual components contribute to the memory's overall degradation. In addition, it is investigated how the application-dependent aging impacts the memory. The results of this work show that, depending on the investigated metric, the peripheral circuitry has a significantly higher contribution to the overall degradation of the memory than the cell array. In addition, the degradation of the memory is shown to be strongly dependent on the application. Overall, the results of this study emphasize that the impact of the peripheral circuitry and the application-dependent aging must be taken into account during design in order to optimally solve SRAM reliability.

Original language	English
Title of host publication	Proceedings - 2020 15th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2020
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE
Number of pages	6
ISBN (Electronic)	9781728154268
DOIs	https://doi.org/10.1109/DTIS48698.2020.9081145
Publication status	Published - 2020
Event	15th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2020 - Marrakesh, Morocco Duration: 1 Apr 2020 → 3 Apr 2020 Conference number: 15

Conference

Conference	15th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2020
Abbreviated title	DTIS 2020
Country/Territory	Morocco
City	Marrakesh
Period	1/04/20 → 3/04/20
Other	Virtual/online event due to COVID-19

Keywords

Aging
Embedded SRAM
Memory
Variability

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10.1109/DTIS48698.2020.9081145

Cite this

@inproceedings{6f21d8b86b5b446fa2c5c893f0058117,

title = "ESRAM Reliability: Why is it still not optimally solved?",

abstract = "As technology scales down, the impact of variability due to process variation and aging increases. In order to guarantee an optimal design with a low failure rate, it is crucial to take into account the impact of these sources of variability. Prior work on SRAM reliability has mainly focused on estimating the impact of this variability on the memory cell array, while the peripheral circuitry and the complete memory circuit have received little attention. This study analyzes the impact of aging on a complete 14nm FinFET SRAM circuit. In this analysis, it is investigated how the memory's individual components contribute to the memory's overall degradation. In addition, it is investigated how the application-dependent aging impacts the memory. The results of this work show that, depending on the investigated metric, the peripheral circuitry has a significantly higher contribution to the overall degradation of the memory than the cell array. In addition, the degradation of the memory is shown to be strongly dependent on the application. Overall, the results of this study emphasize that the impact of the peripheral circuitry and the application-dependent aging must be taken into account during design in order to optimally solve SRAM reliability.",

keywords = "Aging, Embedded SRAM, Memory, Variability",

author = "Daniel Kraak and Mottaqiallah Taouil and Said Hamdioui and Pieter Weckx and Stefan Cosemans and Francky Catthoor",

year = "2020",

doi = "10.1109/DTIS48698.2020.9081145",

language = "English",

booktitle = "Proceedings - 2020 15th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2020",

publisher = "IEEE",

address = "United States",

note = "15th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2020, DTIS 2020 ; Conference date: 01-04-2020 Through 03-04-2020",

}

Kraak, D, Taouil, M , Hamdioui, S, Weckx, P, Cosemans, S & Catthoor, F 2020, ESRAM Reliability: Why is it still not optimally solved? in Proceedings - 2020 15th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2020., 9081145, IEEE, Piscataway, NJ, USA, 15th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2020, Marrakesh, Morocco, 1/04/20. https://doi.org/10.1109/DTIS48698.2020.9081145

ESRAM Reliability: Why is it still not optimally solved? / Kraak, Daniel; Taouil, Mottaqiallah ; Hamdioui, Said et al.
Proceedings - 2020 15th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2020. Piscataway, NJ, USA: IEEE, 2020. 9081145.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - ESRAM Reliability

T2 - 15th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2020

AU - Kraak, Daniel

AU - Taouil, Mottaqiallah

AU - Hamdioui, Said

AU - Weckx, Pieter

AU - Cosemans, Stefan

AU - Catthoor, Francky

N1 - Conference code: 15

PY - 2020

Y1 - 2020

N2 - As technology scales down, the impact of variability due to process variation and aging increases. In order to guarantee an optimal design with a low failure rate, it is crucial to take into account the impact of these sources of variability. Prior work on SRAM reliability has mainly focused on estimating the impact of this variability on the memory cell array, while the peripheral circuitry and the complete memory circuit have received little attention. This study analyzes the impact of aging on a complete 14nm FinFET SRAM circuit. In this analysis, it is investigated how the memory's individual components contribute to the memory's overall degradation. In addition, it is investigated how the application-dependent aging impacts the memory. The results of this work show that, depending on the investigated metric, the peripheral circuitry has a significantly higher contribution to the overall degradation of the memory than the cell array. In addition, the degradation of the memory is shown to be strongly dependent on the application. Overall, the results of this study emphasize that the impact of the peripheral circuitry and the application-dependent aging must be taken into account during design in order to optimally solve SRAM reliability.

AB - As technology scales down, the impact of variability due to process variation and aging increases. In order to guarantee an optimal design with a low failure rate, it is crucial to take into account the impact of these sources of variability. Prior work on SRAM reliability has mainly focused on estimating the impact of this variability on the memory cell array, while the peripheral circuitry and the complete memory circuit have received little attention. This study analyzes the impact of aging on a complete 14nm FinFET SRAM circuit. In this analysis, it is investigated how the memory's individual components contribute to the memory's overall degradation. In addition, it is investigated how the application-dependent aging impacts the memory. The results of this work show that, depending on the investigated metric, the peripheral circuitry has a significantly higher contribution to the overall degradation of the memory than the cell array. In addition, the degradation of the memory is shown to be strongly dependent on the application. Overall, the results of this study emphasize that the impact of the peripheral circuitry and the application-dependent aging must be taken into account during design in order to optimally solve SRAM reliability.

KW - Aging

KW - Embedded SRAM

KW - Memory

KW - Variability

UR - http://www.scopus.com/inward/record.url?scp=85085171031&partnerID=8YFLogxK

U2 - 10.1109/DTIS48698.2020.9081145

DO - 10.1109/DTIS48698.2020.9081145

M3 - Conference contribution

AN - SCOPUS:85085171031

BT - Proceedings - 2020 15th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2020

PB - IEEE

CY - Piscataway, NJ, USA

Y2 - 1 April 2020 through 3 April 2020

ER -

ESRAM Reliability: Why is it still not optimally solved?

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Keywords

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