Evaluating Auto-adaptation Methods for Fine-grained Adaptable Processors

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2 Citations (Scopus)


To achieve energy savings while maintaining adequate performance, system designers and programmers wish to create the best possible match between program behavior and the underlying hardware. Well-known current approaches include DVFS and task migrations in heterogeneous platforms such as big.LITTLE processors. Additionally, processors have been proposed in literature that are able to adapt (parts of) their organization to the workload. These reconfigurations can be managed using hardware monitors, profiling and other compile-time information or a combination of both. Many current solutions are suitable for heterogeneous systems, as migration penalties pose a practical limit to the maximum adaptation frequency, but not for dynamic processors that can adapt much more fine-grained.

In this paper, we present two novel concepts to aid these low-penalty reconfigurable processors - one requiring an ISA extension and one without. Our experimental results show that our approaches enable a dynamic processor to reduce the energy-delay product by up to 25% and on average 10% to 18% compared to the best performing static setups.
Original languageEnglish
Title of host publicationArchitecture of Computing Systems
Subtitle of host publicationARCS 2018; 31st International Conference on Architecture of Computing Systems
EditorsM. Berekovic , R. Buchty, H. Hamann, D. Koch, T. Pionteck
Place of PublicationCham
Number of pages14
ISBN (Electronic)978-3-319-77610-1
ISBN (Print)978-3-319-77609-5
Publication statusPublished - 2018
EventArchitecture of Computing Systems, ARCS 2018: 31th International Conference - Braunschweig, Germany
Duration: 9 Apr 201812 Apr 2018

Publication series

NameLecture Notes in Computer Science, Also part of the Theoretical Computer Science and General Issues book sub series
ISSN (Print)0302-9743


ConferenceArchitecture of Computing Systems, ARCS 2018
Abbreviated titleARCS 2018


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