Evaluation methodology for single electron encoded threshold logic gates

CR Lageweg, SD Cotofana

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

4 Citations (Scopus)
Original languageUndefined/Unknown
Title of host publicationVLSI-SOC: From Systems to Chips
EditorsM. Glesner, R. Reis, L. Indrusiak, V. Mooney, H. Eveking
Place of PublicationNew York, USA
PublisherSpringer
Pages263-280
Number of pages18
ISBN (Print)0-387-33402-5
Publication statusPublished - 2006

Keywords

  • Elektrotechniek
  • Techniek
  • other public output
  • Boekdeel internat.wet

Cite this

Lageweg, CR., & Cotofana, SD. (2006). Evaluation methodology for single electron encoded threshold logic gates. In M. Glesner, R. Reis, L. Indrusiak, V. Mooney, & H. Eveking (Eds.), VLSI-SOC: From Systems to Chips (pp. 263-280). Springer.