Evaluation methodology for single electron encoded threshold logic gates

Research output: Chapter in Book/Conference proceedings/Edited volume › Chapter › Scientific › peer-review

Original language	Undefined/Unknown
Title of host publication	VLSI-SOC: From Systems to Chips
Editors	M. Glesner, R. Reis, L. Indrusiak, V. Mooney, H. Eveking
Place of Publication	New York, USA
Publisher	Springer
Pages	263-280
Number of pages	18
ISBN (Print)	0-387-33402-5
Publication status	Published - 2006

Keywords

@inbook{c58af31cacab4bab959d879408e5f74e,

title = "Evaluation methodology for single electron encoded threshold logic gates",

keywords = "Elektrotechniek, Techniek, other public output, Boekdeel internat.wet",

author = "CR Lageweg and SD Cotofana",

year = "2006",

language = "Undefined/Unknown",

isbn = "0-387-33402-5",

pages = "263--280",

editor = "M. Glesner and R. Reis and L. Indrusiak and V. Mooney and H. Eveking",

booktitle = "VLSI-SOC: From Systems to Chips",

publisher = "Springer",

address = "United States",

}

TY - CHAP

T1 - Evaluation methodology for single electron encoded threshold logic gates

AU - Lageweg, CR

AU - Cotofana, SD

PY - 2006

Y1 - 2006

KW - Elektrotechniek

KW - Techniek

KW - other public output

KW - Boekdeel internat.wet

M3 - Chapter

SN - 0-387-33402-5

SP - 263

EP - 280

BT - VLSI-SOC: From Systems to Chips

A2 - Glesner, M.

A2 - Reis, R.

A2 - Indrusiak, L.

A2 - Mooney, V.

A2 - Eveking, H.

PB - Springer

CY - New York, USA

ER -