Memristive devices have become promising candidates to complement and/or replace the CMOS technology, due to their CMOS manufacturing process compatibility, zero standby power consumption, high scalability, as well as their capability to implement high-density memories and new computing paradigms. Despite these advantages, memristive devices are also susceptible to manufacturing defects that may cause different faulty behaviors not observed in CMOS technology, significantly increasing the manufacturing test complexity. This work proposes a Design-for-Testability (DfT) strategy based on the introduction of a on-chip sensor that measures the current consumption of Resistive Random Access Memories (RRAMs) cells to provide the detection of unique faults. The new On-Chip Sensor (ON_CS) was validated using a case study 3×3 RRAM cell array with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library. Experimental results show that the proposed DfT strategy is able to detect not only traditional faults, but also unique faults that can affect RRAM cells. Finally, this paper proposes an DfT strategy that can detect unique faults with an unique operation and can be used during the normal operation of a RRAM.
|Title of host publication||Proceedings of the 2022 IEEE 23rd Latin American Test Symposium (LATS)|
|Number of pages||6|
|Publication status||Published - 2022|
|Event||2022 IEEE 23rd Latin American Test Symposium (LATS) - Montevideo, Uruguay|
Duration: 5 Sep 2022 → 8 Sep 2022
|Conference||2022 IEEE 23rd Latin American Test Symposium (LATS)|
|Period||5/09/22 → 8/09/22|
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- Unique Faults
- On-Chip Sensor