Exploring test opportunities for memory and interconnects in 3D ICs

M Taouil, M Lefter, S Hamdioui

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Original languageEnglish
Title of host publicationInternational design & test symposium
Editors s.n.
Place of Publications.l.
Publishers.n.
Pages1-6
Number of pages6
Publication statusPublished - 2012
EventIDT 2012 - s.l.
Duration: 15 Dec 201217 Dec 2012

Publication series

Name
Publishers.n.

Conference

ConferenceIDT 2012
Period15/12/1217/12/12

Cite this

Taouil, M., Lefter, M., & Hamdioui, S. (2012). Exploring test opportunities for memory and interconnects in 3D ICs. In s.n. (Ed.), International design & test symposium (pp. 1-6). s.n..