Exponential extended flash time-to-digital converter

Peng Chen; Robert Bogdan Staszewski

doi:10.1109/EBCCSP.2016.7605281

Exponential extended flash time-to-digital converter

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

Abstract

The digital-to-time converter (DTC)-based all-digital phase locked loop (ADPLL) attracts more and more attention due to its ultra-lower power consumption characteristic [1]. With DTC, the time-to-digital converter's (TDC) requirements are relaxed, not only for its range but also for its nonlinearity. However, the shortened TDC range, which is less than one digital controlled oscillator (DCO) output period in the new architecture makes the settling time longer and the TDC gain calibration difficult. This work introduces a technique to extend the TDC range by 16 times to accelerate the settling process, while the extended part can be disabled when ADPLL is in lock. Furthermore, the TDC gain calibration is easier.

Original language	English
Title of host publication	2016 2nd International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP)
Subtitle of host publication	Proceedings
Publisher	IEEE
Pages	1-4
Number of pages	4
ISBN (Electronic)	978-1-5090-4196-1
ISBN (Print)	978-1-5090-4197-8
DOIs	https://doi.org/10.1109/EBCCSP.2016.7605281
Publication status	Published - 20 Oct 2016
Externally published	Yes
Event	2nd International Conference on Event-Based Control, Communication, and Signal Processing, EBCCSP 2016 - Krakow, Poland Duration: 13 Jun 2016 → 15 Jun 2016

Conference

Conference	2nd International Conference on Event-Based Control, Communication, and Signal Processing, EBCCSP 2016
Country/Territory	Poland
City	Krakow
Period	13/06/16 → 15/06/16

Keywords

DLL
DTC-based ADPLL
exponential
TDC
two stages

Access to Document

10.1109/EBCCSP.2016.7605281

Cite this

@inproceedings{1fa0085002d64258b8e776edc866df67,

title = "Exponential extended flash time-to-digital converter",

abstract = "The digital-to-time converter (DTC)-based all-digital phase locked loop (ADPLL) attracts more and more attention due to its ultra-lower power consumption characteristic [1]. With DTC, the time-to-digital converter's (TDC) requirements are relaxed, not only for its range but also for its nonlinearity. However, the shortened TDC range, which is less than one digital controlled oscillator (DCO) output period in the new architecture makes the settling time longer and the TDC gain calibration difficult. This work introduces a technique to extend the TDC range by 16 times to accelerate the settling process, while the extended part can be disabled when ADPLL is in lock. Furthermore, the TDC gain calibration is easier.",

keywords = "DLL, DTC-based ADPLL, exponential, TDC, two stages",

author = "Peng Chen and Staszewski, {Robert Bogdan}",

year = "2016",

month = oct,

day = "20",

doi = "10.1109/EBCCSP.2016.7605281",

language = "English",

isbn = "978-1-5090-4197-8",

pages = "1--4",

booktitle = "2016 2nd International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP)",

publisher = "IEEE",

address = "United States",

note = "2nd International Conference on Event-Based Control, Communication, and Signal Processing, EBCCSP 2016 ; Conference date: 13-06-2016 Through 15-06-2016",

}

Chen, P & Staszewski, RB 2016, Exponential extended flash time-to-digital converter. in 2016 2nd International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP) : Proceedings., 7605281, IEEE, pp. 1-4, 2nd International Conference on Event-Based Control, Communication, and Signal Processing, EBCCSP 2016, Krakow, Poland, 13/06/16. https://doi.org/10.1109/EBCCSP.2016.7605281

TY - GEN

T1 - Exponential extended flash time-to-digital converter

AU - Chen, Peng

AU - Staszewski, Robert Bogdan

PY - 2016/10/20

Y1 - 2016/10/20

N2 - The digital-to-time converter (DTC)-based all-digital phase locked loop (ADPLL) attracts more and more attention due to its ultra-lower power consumption characteristic [1]. With DTC, the time-to-digital converter's (TDC) requirements are relaxed, not only for its range but also for its nonlinearity. However, the shortened TDC range, which is less than one digital controlled oscillator (DCO) output period in the new architecture makes the settling time longer and the TDC gain calibration difficult. This work introduces a technique to extend the TDC range by 16 times to accelerate the settling process, while the extended part can be disabled when ADPLL is in lock. Furthermore, the TDC gain calibration is easier.

AB - The digital-to-time converter (DTC)-based all-digital phase locked loop (ADPLL) attracts more and more attention due to its ultra-lower power consumption characteristic [1]. With DTC, the time-to-digital converter's (TDC) requirements are relaxed, not only for its range but also for its nonlinearity. However, the shortened TDC range, which is less than one digital controlled oscillator (DCO) output period in the new architecture makes the settling time longer and the TDC gain calibration difficult. This work introduces a technique to extend the TDC range by 16 times to accelerate the settling process, while the extended part can be disabled when ADPLL is in lock. Furthermore, the TDC gain calibration is easier.

KW - DLL

KW - DTC-based ADPLL

KW - exponential

KW - TDC

KW - two stages

UR - http://www.scopus.com/inward/record.url?scp=84998780423&partnerID=8YFLogxK

U2 - 10.1109/EBCCSP.2016.7605281

DO - 10.1109/EBCCSP.2016.7605281

M3 - Conference contribution

AN - SCOPUS:84998780423

SN - 978-1-5090-4197-8

SP - 1

EP - 4

BT - 2016 2nd International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP)

PB - IEEE

T2 - 2nd International Conference on Event-Based Control, Communication, and Signal Processing, EBCCSP 2016

Y2 - 13 June 2016 through 15 June 2016

ER -

Exponential extended flash time-to-digital converter

Abstract

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this