Exponential extended flash time-to-digital converter

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Abstract

The digital-to-time converter (DTC)-based all-digital phase locked loop (ADPLL) attracts more and more attention due to its ultra-lower power consumption characteristic [1]. With DTC, the time-to-digital converter's (TDC) requirements are relaxed, not only for its range but also for its nonlinearity. However, the shortened TDC range, which is less than one digital controlled oscillator (DCO) output period in the new architecture makes the settling time longer and the TDC gain calibration difficult. This work introduces a technique to extend the TDC range by 16 times to accelerate the settling process, while the extended part can be disabled when ADPLL is in lock. Furthermore, the TDC gain calibration is easier.

Original languageEnglish
Title of host publication2016 2nd International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP)
Subtitle of host publicationProceedings
PublisherIEEE
Pages1-4
Number of pages4
ISBN (Electronic)978-1-5090-4196-1
ISBN (Print)978-1-5090-4197-8
DOIs
Publication statusPublished - 20 Oct 2016
Externally publishedYes
Event2nd International Conference on Event-Based Control, Communication, and Signal Processing, EBCCSP 2016 - Krakow, Poland
Duration: 13 Jun 201615 Jun 2016

Conference

Conference2nd International Conference on Event-Based Control, Communication, and Signal Processing, EBCCSP 2016
CountryPoland
CityKrakow
Period13/06/1615/06/16

Keywords

  • DLL
  • DTC-based ADPLL
  • exponential
  • TDC
  • two stages

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