Extraction, Optimization and Failure Detection Application of Parasitic Inductance for High-Frequency SiC Power Devices

Minghui Yun, Kailin Zhang , Miao Cai, Yiren Yang , Changqi Feng, Song Wei, Daoguo Yang, Guoqi Zhang

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Abstract

Silicon carbide (SiC) is a third-generation semiconductor material with many advantages, such as high thermal conductivity, high critical breakdown voltage, and high saturated electron drift velocity, which can increase the operating frequency of the power conversion system to more than 100kHz. In the high-frequency, the parasitic effect will significantly reduce the switching speed of the power devices, increase power consumption and influence the uniformity of current distribution. In this paper, we established the calculation nodes of each part of the SiC-MOSFET Half-bridge power module and used ANSYS Q3D software to extract the parasitic parameters. Die-Die, Die-DBC-1, Die-DBC-2 and hybrid interconnect package structures were designed to optimize the parasitic inductance. Simulation results indicated that the chip-DBC-1 structure can reduce the parasitic inductance about 30% compared with Chip-Chip structure and effectively control the uniformity of current density on two parallel diode chips (ΔLdiode <0.1%). In the meantime, an 3D model of partial bond wires broken were designed to get further insight into the variation of parasitic inductances. The correlation mechanism between the partial bond wires broken and inductance change of the D-S terminals current path was studied. The results showed that as the number of broken bond wires increases, the inductance of D-S terminals current path was increased gradually. Finally, by using two-port S-parameters measurement method to extract the inductances of the discrete power device, the experimental results indicated that when one or two bond wires were broken, the inductance of D-S terminals current path increased by 4.69% and 15.69%, respectively. Overview, a risk evaluation method for SiC power devices based on the variation of the parasitic parameters of the bond wire was established.
Original languageEnglish
Title of host publication2021 22nd International Conference on Electronic Packaging Technology (ICEPT)
Subtitle of host publicationProceedings
PublisherIEEE
Number of pages5
ISBN (Electronic)978-1-6654-1391-6
ISBN (Print)978-1-6654-1392-3
DOIs
Publication statusPublished - 2021
EventICEPT 2021: 22nd International Conference on Electronic Packaging Technology - Xiamen, China
Duration: 14 Sep 202117 Sep 2021
Conference number: 22nd

Conference

ConferenceICEPT 2021
CountryChina
CityXiamen
Period14/09/2117/09/21

Keywords

  • SiC power devices
  • Bond wires
  • Parasitic
  • inductance
  • Packaging

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