Facing the challenge of designing for Cu/low-k reliability

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27 Citations (Scopus)

Abstract

With the decrease of the feature size to 90 nm and lower new materials are introduced in the waferfabs. Copper replaced aluminium and low-k dielectrics served as a better isolator. But this change has serious consequences for the structural integrity of the IC interconnects after processing and package manufacturing. Due to the fact that the new materials have substantially different thermo-mechanical properties, sufficient reliability performance for the IC package becomes a key factor. This paper presents solutions for the reliability problems faced due to the introduction of Cu/low-k as a consequence of the packaging processes. The packaging processes that significantly endanger the Cu/low-k integrity are probing, wire bonding, and moulding. Examples of the reliability issues are presented; these are deep probe marks, metal peel off, and/or pulled-off IC layers. To solve these issues, packaging process conditions and material properties are tuned to better fit with the Cu/low-k technology. Hopefully, the lessons learned and the newly developed state-of-the-art modelling and experimental techniques will enable the industry to release the lower node technologies such as CMOS065.
Original languageUndefined/Unknown
Pages (from-to)1969-1974
Number of pages6
JournalMicroelectronics Reliability
Volume47
Publication statusPublished - 2007

Keywords

  • academic journal papers
  • CWTS JFIS < 0.75

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