Fan-out enabled spin wave majority gate

Abdulqader Mahmoud*, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, Said Hamdioui, Sorin Cotofana

*Corresponding author for this work

Research output: Contribution to journalArticleScientificpeer-review

25 Citations (Scopus)
98 Downloads (Pure)


By its very nature, Spin Wave (SW) interference provides intrinsic support for Majority logic function evaluation. Due to this and the fact that the 3-input Majority (MAJ3) gate and the inverter constitute a universal Boolean logic gate set, different MAJ3 gate implementations have been proposed. However, they cannot be directly utilized for the construction of larger SW logic circuits as they lack a key cascading mechanism, i.e., fanout capability. In this paper, we introduce a novel ladder-shaped SW MAJ3 gate design able to provide a maximum fanout of 2 (FO2). The proper gate functionality is validated by means of micromagnetic simulations, which also demonstrate that the amplitude mismatch between the two outputs is negligible, proving that an FO2 is properly achieved. Additionally, we evaluate the gate area and compare it with SW state-of-the-art and 15 nm CMOS counterparts working under the same conditions. Our results indicate that the proposed structure requires a 12× less area than the 15 nm CMOS MAJ3 gate and that at the gate level, the fanout capability results in 16% area savings, when compared to the state-of-the-art SW majority gate counterparts.

Original languageEnglish
Article number035119
Pages (from-to) 035119-1 - 035119-6
Number of pages6
JournalAIP Advances
Issue number3
Publication statusPublished - 2020


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