Fatigue Damage Assessment of LED Chip Scale Packages with Finite Element Simulation

Jiajie Fan; Aihua Hu; Michael Pecht; Wei Chen; Xuejun Fan; Dan Xu; Guoqi Zhang

doi:10.1109/ICEPT.2018.8480748

Fatigue Damage Assessment of LED Chip Scale Packages with Finite Element Simulation

Jiajie Fan^*, Aihua Hu, Michael Pecht, Wei Chen, Xuejun Fan, Dan Xu, Guoqi Zhang

^*Corresponding author for this work

Electronic Components, Technology and Materials

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

3 Citations (Scopus)

Abstract

As one of solid state lighting sources, wafer-level chip scale Light Emitting Diode (LED) packages has gained much attention, because of its compact size, high power and high optical performance. For this package to be effective, the solder layer plays the critical role in heat dissipation, mechanical support and electrical conductivity. Among all types of solder materials, Sn-3.0Ag-0.5Cu (SAC305) solder alloy is considered as one of best chip-attachment candidates due to its acceptable cost, good solderability, and favorable shear strength. However, such solder connections are prone to fatigue over time due to thermal or power cycling. This paper models the wafer level chip scale LEDs soldered on both aluminum oxide and aluminum substrates with SAC305 solder alloy. Thermal cycling conditions are simulated to assess the fatigue damage of the solder interconnection. Von Mises stress and plastic work density are utilized to represent the fatigue damage per cycle by using finite element analysis (FEA) method. Important design considerations include the effects of LED chip substrate, thickness of the solder interconnections, void ratio in the solder connections and PCB substrate. The result is a set of fatigue damage accumulation metrics.

Original language	English
Title of host publication	Proceedings - 2018 19th International Conference on Electronic Packaging Technology, ICEPT 2018
Editors	F. Xiao, J. Wang, L. Chen, T. Ye
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	1642-1648
Number of pages	7
ISBN (Electronic)	978-1-5386-6386-8
DOIs	https://doi.org/10.1109/ICEPT.2018.8480748
Publication status	Published - 2018
Event	ICEPT 2018: 19th International Conference on Electronic Packaging Technology - Shanghai, China Duration: 8 Aug 2018 → 11 Aug 2018 Conference number: 19

Conference

Conference	ICEPT 2018
Country/Territory	China
City	Shanghai
Period	8/08/18 → 11/08/18

Keywords

finite element model
flip chip
Light-emitting diodes
solder layer
WLCSP

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10.1109/ICEPT.2018.8480748

Cite this

Fan, J., Hu, A., Pecht, M., Chen, W., Fan, X., Xu, D., & Zhang, G. (2018). Fatigue Damage Assessment of LED Chip Scale Packages with Finite Element Simulation. In F. Xiao, J. Wang, L. Chen, & T. Ye (Eds.), Proceedings - 2018 19th International Conference on Electronic Packaging Technology, ICEPT 2018 (pp. 1642-1648). Article 8480748 IEEE. https://doi.org/10.1109/ICEPT.2018.8480748

@inproceedings{924a292206354b9a85f2394c6740194b,

title = "Fatigue Damage Assessment of LED Chip Scale Packages with Finite Element Simulation",

abstract = "As one of solid state lighting sources, wafer-level chip scale Light Emitting Diode (LED) packages has gained much attention, because of its compact size, high power and high optical performance. For this package to be effective, the solder layer plays the critical role in heat dissipation, mechanical support and electrical conductivity. Among all types of solder materials, Sn-3.0Ag-0.5Cu (SAC305) solder alloy is considered as one of best chip-attachment candidates due to its acceptable cost, good solderability, and favorable shear strength. However, such solder connections are prone to fatigue over time due to thermal or power cycling. This paper models the wafer level chip scale LEDs soldered on both aluminum oxide and aluminum substrates with SAC305 solder alloy. Thermal cycling conditions are simulated to assess the fatigue damage of the solder interconnection. Von Mises stress and plastic work density are utilized to represent the fatigue damage per cycle by using finite element analysis (FEA) method. Important design considerations include the effects of LED chip substrate, thickness of the solder interconnections, void ratio in the solder connections and PCB substrate. The result is a set of fatigue damage accumulation metrics.",

keywords = "finite element model, flip chip, Light-emitting diodes, solder layer, WLCSP",

author = "Jiajie Fan and Aihua Hu and Michael Pecht and Wei Chen and Xuejun Fan and Dan Xu and Guoqi Zhang",

year = "2018",

doi = "10.1109/ICEPT.2018.8480748",

language = "English",

pages = "1642--1648",

editor = "F. Xiao and J. Wang and L. Chen and T. Ye",

booktitle = "Proceedings - 2018 19th International Conference on Electronic Packaging Technology, ICEPT 2018",

publisher = "IEEE",

address = "United States",

note = "ICEPT 2018 : 19th International Conference on Electronic Packaging Technology ; Conference date: 08-08-2018 Through 11-08-2018",

}

Fan, J, Hu, A, Pecht, M, Chen, W, Fan, X, Xu, D & Zhang, G 2018, Fatigue Damage Assessment of LED Chip Scale Packages with Finite Element Simulation. in F Xiao, J Wang, L Chen & T Ye (eds), Proceedings - 2018 19th International Conference on Electronic Packaging Technology, ICEPT 2018., 8480748, IEEE, Piscataway, NJ, pp. 1642-1648, ICEPT 2018, Shanghai, China, 8/08/18. https://doi.org/10.1109/ICEPT.2018.8480748

Fatigue Damage Assessment of LED Chip Scale Packages with Finite Element Simulation. / Fan, Jiajie; Hu, Aihua; Pecht, Michael et al.
Proceedings - 2018 19th International Conference on Electronic Packaging Technology, ICEPT 2018. ed. / F. Xiao; J. Wang; L. Chen; T. Ye. Piscataway, NJ: IEEE, 2018. p. 1642-1648 8480748.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Fatigue Damage Assessment of LED Chip Scale Packages with Finite Element Simulation

AU - Fan, Jiajie

AU - Hu, Aihua

AU - Pecht, Michael

AU - Chen, Wei

AU - Fan, Xuejun

AU - Xu, Dan

AU - Zhang, Guoqi

N1 - Conference code: 19

PY - 2018

Y1 - 2018

N2 - As one of solid state lighting sources, wafer-level chip scale Light Emitting Diode (LED) packages has gained much attention, because of its compact size, high power and high optical performance. For this package to be effective, the solder layer plays the critical role in heat dissipation, mechanical support and electrical conductivity. Among all types of solder materials, Sn-3.0Ag-0.5Cu (SAC305) solder alloy is considered as one of best chip-attachment candidates due to its acceptable cost, good solderability, and favorable shear strength. However, such solder connections are prone to fatigue over time due to thermal or power cycling. This paper models the wafer level chip scale LEDs soldered on both aluminum oxide and aluminum substrates with SAC305 solder alloy. Thermal cycling conditions are simulated to assess the fatigue damage of the solder interconnection. Von Mises stress and plastic work density are utilized to represent the fatigue damage per cycle by using finite element analysis (FEA) method. Important design considerations include the effects of LED chip substrate, thickness of the solder interconnections, void ratio in the solder connections and PCB substrate. The result is a set of fatigue damage accumulation metrics.

AB - As one of solid state lighting sources, wafer-level chip scale Light Emitting Diode (LED) packages has gained much attention, because of its compact size, high power and high optical performance. For this package to be effective, the solder layer plays the critical role in heat dissipation, mechanical support and electrical conductivity. Among all types of solder materials, Sn-3.0Ag-0.5Cu (SAC305) solder alloy is considered as one of best chip-attachment candidates due to its acceptable cost, good solderability, and favorable shear strength. However, such solder connections are prone to fatigue over time due to thermal or power cycling. This paper models the wafer level chip scale LEDs soldered on both aluminum oxide and aluminum substrates with SAC305 solder alloy. Thermal cycling conditions are simulated to assess the fatigue damage of the solder interconnection. Von Mises stress and plastic work density are utilized to represent the fatigue damage per cycle by using finite element analysis (FEA) method. Important design considerations include the effects of LED chip substrate, thickness of the solder interconnections, void ratio in the solder connections and PCB substrate. The result is a set of fatigue damage accumulation metrics.

KW - finite element model

KW - flip chip

KW - Light-emitting diodes

KW - solder layer

KW - WLCSP

UR - http://www.scopus.com/inward/record.url?scp=85056402612&partnerID=8YFLogxK

U2 - 10.1109/ICEPT.2018.8480748

DO - 10.1109/ICEPT.2018.8480748

M3 - Conference contribution

AN - SCOPUS:85056402612

SP - 1642

EP - 1648

BT - Proceedings - 2018 19th International Conference on Electronic Packaging Technology, ICEPT 2018

A2 - Xiao, F.

A2 - Wang, J.

A2 - Chen, L.

A2 - Ye, T.

PB - IEEE

CY - Piscataway, NJ

T2 - ICEPT 2018

Y2 - 8 August 2018 through 11 August 2018

ER -

Fatigue Damage Assessment of LED Chip Scale Packages with Finite Element Simulation

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