TY - JOUR
T1 - Fault-induced current limitation control for grid-forming inverters: A framework for rapid grid code compliance
AU - Pal, Arjita
AU - Achlerkar, Pankaj Dilip
AU - Panigrahi, Bijaya Ketan
PY - 2025/5
Y1 - 2025/5
N2 - This paper presents a current limitation scheme for a grid-forming inverter-based resource (IBR). The proposed controller allows the IBR to be integrated into distribution networks while ensuring rapid overcurrent protection and adherence to grid codes for low and medium-voltage grids. The method employs event-triggered time control logic that deactivates grid-forming inverter (GFMI)’s outer power control loop and uses the angle of the current reference as a variable to determine the current injection into the grid during faults. It also monitors the duration the IBR should endure a fault before deciding to trip. The performance of the proposed controller in limiting current is assessed through time-domain simulations after a 100% grid voltage sag. The controller demonstrates a significant improvement in the fault-ride-through (FRT) characteristics and post-fault synchronization dynamics of the GFMI. The study also explores and compares the proposed framework with existing strategies of virtual impedance (VI), current saturation (CS), and priority-based current saturation (PCS). The effectiveness of the proposed controller is also validated through experiments conducted on a power-hardware-in-the-loop (PHiL) test bench that explores the interactions between a physical GFMI and a simulated power grid under various critical operating scenarios like a severe symmetrical fault at the point of common coupling (PCC).
AB - This paper presents a current limitation scheme for a grid-forming inverter-based resource (IBR). The proposed controller allows the IBR to be integrated into distribution networks while ensuring rapid overcurrent protection and adherence to grid codes for low and medium-voltage grids. The method employs event-triggered time control logic that deactivates grid-forming inverter (GFMI)’s outer power control loop and uses the angle of the current reference as a variable to determine the current injection into the grid during faults. It also monitors the duration the IBR should endure a fault before deciding to trip. The performance of the proposed controller in limiting current is assessed through time-domain simulations after a 100% grid voltage sag. The controller demonstrates a significant improvement in the fault-ride-through (FRT) characteristics and post-fault synchronization dynamics of the GFMI. The study also explores and compares the proposed framework with existing strategies of virtual impedance (VI), current saturation (CS), and priority-based current saturation (PCS). The effectiveness of the proposed controller is also validated through experiments conducted on a power-hardware-in-the-loop (PHiL) test bench that explores the interactions between a physical GFMI and a simulated power grid under various critical operating scenarios like a severe symmetrical fault at the point of common coupling (PCC).
UR - http://www.scopus.com/inward/record.url?scp=85216637884&partnerID=8YFLogxK
U2 - 10.1016/j.epsr.2025.111471
DO - 10.1016/j.epsr.2025.111471
M3 - Article
SN - 0378-7796
VL - 242
JO - Electric Power Systems Research
JF - Electric Power Systems Research
M1 - 111471
ER -